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Figure 1: TEBA0841-01 Block Diagram.

Main Components

      Image Modified          Image Modified

Figure 2: TEBA0841-01 Carrier Board.

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Following table gives a summary of the available I/O's, interfaces and differential pairs of the B2B connectors JB1, JB2 and JB3:

Table 1: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

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Following table gives a summary of the pin-assignment, available interfaces and functional I/O's of the pin headers:

Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.

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The pin-assignment of the SFP connector is in detail as fellows:

Table 3: SFP+ connector pin-assignment.

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The MGT lane pins are bridged on-board as fellows, if 4 x 5 SoM TE0741 is mounted on carrier board:

Table 4: Looped-backed MGT-lanes for mounted 4 x 5 SoM TE0741.

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JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JX1 and pin header J3. With the TE0790 XMOD USB2.0 to JTAG adapter, the device of the mounted SoM can be programed via USB2.0 interface.

Table 5: JTAG interface signals.

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UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

Table 6: UART interface signals.

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The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:

Table 7: SD IO interface signals.

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Following table gives an overview of the USB2.0 interface signals:

Table 8: USB2.0 interface signals and connections.

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Following table describes the signals and interfaces of the XMOD header JX1 and pin header J3:

Table 9: JTAG/UART header signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the DIP-switch with the setting:

Table 10: XMOD adapter board DIP-switch positions for voltage configuration.

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The on-board LEDs are available to the user and can be used to indicate system status and activities:

Figure 11: On-board LEDs

VCCIO Selection Jumper

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TE 4 x 5 Modules have a standard assignment of PL-bank I/O voltages on their B2B connectors, which will be fed with I/O voltage from base-board.

Table 12: Base-board PL-bank I/O voltages VCCIOA and VCCIOD

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Following table describes how to configure the base-board supply-voltages by jumpers:

Table 13: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.

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Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 14: Typical power consumption.

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The external power-supply can be connected to the board by the following pins:

Table 15: Connector pins capable for external 3.3V power supply

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The voltage direction of the power rails is from board and on-board connectors' view:

Table 16: Power pin description of B2B module connector.

Table 17: Power Pin description of on-board connector.

Table 18: Power Pin description of VCCIO selection jumper pin header.

Table 19: Power pin description of peripheral connector.

Table 20: Power pin description of XMOD/JTAG Connector.

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Technical Specifications

Absolute Maximum Ratings

Table 21: Board absolute maximum ratings.

Recommended Operating Conditions

Table 22: Module recommended operating conditions.

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Hardware Revision History

Table 23: Module hardware revision history.

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Table 24: Document change history.

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