Page History
...
DIP-Switches
There are two 4-bit DIP Switches -witches present on the TEBF0808 carrier board to configure options and set parameters. The table below following section describes the functionalities of the particular switches.
...
Table below describes the functionalities of the switches of DIP-switch S4 at their each single positions:
| DIP-switch S4 | Position ON | Position OFF | Notes |
|---|---|---|---|
| S4-1 | PUDC_B is Low | PUDC_B is HIGH | Internal pull-up resistors during configuration are enabled at ON-position, means I/O's are 3-stated until configuration of the FPGA completes. |
| S4-2 | x | x | not connected |
| S4-3 | SC CPLDs' JTAG enabled | SC CPLDs' JTAG disabled | JTAG interface is enabled on both SC CPLDs, as this CPLDs are configured in a casdaced JTAG chain. |
| S4-4 | DC-DC converter U18 (5V) enabled | DC-DC converter U18 (5V) not manually enabled | In OFF-position, the DC-DC-converter will be still enabled by the Enable-signal ('5V_EN') of SC CDPD U39 (wired-OR circuit). |
...
The boot mode of the mounted Ultrascale+ Zynq MPSoC modules module will be set in current SC CPLD U39 firmware version as fellow described in the table below:
...
Overview
Content Tools