Page History

Page properties

hidden	true
id	Comments

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Date	Version	Changes	Author
2023-12-14	3.1.17	updated according to Vivado 2023.2	ma
2023-06-13	3.1.16	Design flow: added alternative programming files in Petalinux added chapter FSBL Patch in Software Design - Petalinux	ma
2023-06-01	3.1.15	removed u-boot.dtb from Design flow	ma
2023-06-01	3.1.14	expandable lists for revision history and supported hardware	wh
2022-01-14	3.1.9	extended notes for microblaze boot process with linux add u.boot.dtb to petalinux notes add dtb to prebuilt content replace 20.2 with 21.2	jh
2021-06-28	3.1.8	added boot process for Microblaze minor typos, formatting	ma
2021-06-01	3.1.7	carrier reference note	jh
2021-05-04	3.1.6	removed zynq_ from zynq_fsbl	ma
2021-04-28	3.1.5	added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export minor typos, formatting	ma
2021-04-27	3.1.4	Version History changed from list to table Design flow removed step 5 from Design flow changed link from TE Board Part Files to Vivado Board Part Flow changed cmd shell from picture to codeblock added hidden template for "Copy PetaLinux build image files", depending from hardware added hidden template for "Power on PCB", depending from hardware Usage update of boot process Requirements - Hardware added "^*used as reference" for hardware requirements all placed a horizontal separation line under each chapter heading changed title-alignment for tables from left to center all tables added "<project folder>\board_files" in Vivado design sources	ma
	3.1.3	Design Flow formatting Launch formatting	ma
	3.1.2	minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.src description added USB for programming	ma
	3.1.1	swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow	ma
	3.1	Fix problem with pdf export and side scroll bar update 19.2 to 20.2 add prebuilt content option
	3.0	add fix table of content add table size as macro removed page initial creator

Custom_table_size_100

Page properties

hidden	true
id	Comments

Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default style
widths sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

...

Overview

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Zynq PS Design

- Redirects

Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.

Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Key Features

Page properties

hidden	true
id	Comments

Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 20212023.2 PetaLinux SD ETH (use EEPROM MAC) USB I2C RTC VIO PHY LED FSBL for EEPROM MAC and CPLD access / petalinux patch Special FSBL for QSPI Programming

Revision History

Page properties

hidden	true
id	Comments

Notes :

add every update file on the download
add design changes on description

widths

Expand

title	Expand List

Scroll Title

anchor	Table_DRH
title-alignment	center
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default

style


sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Vivado	Project Built	Authors	Description

2022

2024-

02

01-

02

25

2021

2023.2

TE0720-test_board-vivado_

2021

2023.2-build_

11

4_

20220202131818

20240124111006.zip
TE0720-test_board_noprebuilt-vivado_

2021

2023.2-build_

11

4_

20220202131838

20240124111006.zip

Manuela Strücker

bugfix "os" folder
updated Petalinux config
- added QSPI Partition for bootscr file

Device-Tree patch for single core variants

2024

2022

-01-

25

22

2021

2023.2

TE0720-test_board-vivado_

2021

2023.2-build_

10

4_

20220125090947

20240122114822.zip
TE0720-test_board_noprebuilt-vivado_

2021

2023.2-build_

10

4_

20220125090947

20240122114822.zip

Manuela Strücker

2021

2023.2 update

2021

2023-

12

07-

15

19

2020

2022.2

TE0720-test_board-vivado_

2020

2022.2-build_

9

2_

20211215123235

20230719115741.zip
TE0720-test_board_noprebuilt-vivado_

2020

2022.2-build_

9

2_

20211215123235_production

20230719115741.zip

Manuela Strücker

new Assembly variants

Waldemar Hanemann	bugfix -boot up on first power up only. qspi x4 - device tree node entry
2023-05-31	2022

2021-11-292020

.2	TE0720-test_board-vivado_

2020

2022.2-build_

9

1_

20211129062154

20230531192416.zip
TE0720-test_board_noprebuilt-vivado_

2020

2022.2-build_

9

1_

20211129062716

20230531192416.zip

Manuela Strücker

new Assembly variants

2021-07-19

Waldemar Hanemann	2022.2 update
2022-02-02	2021

2020

.2	TE0720-test_board

_noprebuilt

-vivado_

2020

2021.2-build_

6

11_

20210719131800

20220202131818.zip
TE0720-test_board_noprebuilt-vivado_

2020

2021.2-build_

6

11_

20210719131744

20220202131838.zip

Manuela Strücker

boot.scr file updated for 256 MB QSPI flash size variants

bugfix "os" folder updated Petalinux config added QSPI Partition for bootscr file
2022-01-25	2021

2021-04-302020

.2	TE0720-test_board

_noprebuilt

-vivado_

2020

2021.2-build_

5

10_

20210430085624

20220125090947.zip
TE0720-test_board_noprebuilt-vivado_

2020

2021.2-build_

5

10_

20210430085609

20220125090947.zip

Manuela Strücker

update board files

update boot.scr file

2021.2 update

2021-

04

12-

01

15

2020.2

TE0720-test_board

_noprebuilt

-vivado_2020.2-build_

4

9_

20210401140444

20211215123235.zip
TE0720-test_board-vivado_2020.2-build_9_

4

20211215123235_

20210401140432

production.zip

John Hartfielbugfix missing binaries+ boot.scr file(supports now QSPI and SD boot with image.ub on SD)

Manuela Strücker	new Assembly variants
2021-

02

11-

17

29

2020.2

TE0720-test_board

_noprebuilt

-vivado_2020.2-build_

2

9_

20210217064925

20211129062154.zip
TE0720-test_board_noprebuilt-vivado_2020.2-build_

2

9_

20210217064913

20211129062716.zip

John Hartfiel

2020.2 update
add boot.scr file
petalinux fsbl patch (beta-version)

Manuela Strücker	new Assembly variants
2021-07-19	2020

2020-03-252019

.2	TE0720-test_board_noprebuilt-vivado_

2019

2020.2-build_

8

6_

20200325075220

20210719131800.zip
TE0720-test_board-vivado_

2019

2020.2-build_

8

6_

20200325075301

20210719131744.zip

John Hartfiel

script update

2020-01-22

Manuela Strücker	boot.scr file updated for 256 MB QSPI flash size variants
2021-04-30	2020

2019

.2	TE0720-test_board_noprebuilt-vivado_

2019

2020.2-build_

3

5_

20200122154933

20210430085624.zip
TE0720-test_board

_noprebuilt

-vivado_

2019

2020.2-build_

3

5_

20200122154951

20210430085609.zip

John Hartfiel

script update for linux user

2020-01-14

Manuela Strücker	update board files update boot.scr file
2021-04-01	2020

2019

.2	TE0720-test_board_noprebuilt-vivado_

2019

2020.2-build_

3

4_

20200114090828

20210401140444.zip
TE0720-test_board

_noprebuilt

-vivado_

2019

2020.2-build_

3

4_

20200114090837

20210401140432.zip

John Hartfiel

Vitis script updates (include linux domain and prebuilt linux files for vitis)
prebuilt binary export on selection guide

bugfix missing binaries+ boot.scr file(supports now QSPI and SD boot with image.ub on SD)
2021-02-17	2020

2019-12-182019

.2	TE0720-test_board_noprebuilt-vivado_

2019

2020.2-build_

1

2_

20191218151902

20210217064925.zip
TE0720-test_board

_noprebuilt

-vivado_

2019

2020.2-build_

1

2_

20191218152732

20210217064913.zip

John Hartfiel

2019

2020.2 update

Vitis support

2019

add boot.scr file
petalinux fsbl patch (beta-version)

2020-03-

04

25

2018

2019.

3

2	TE0720-test_board_noprebuilt-vivado_

2018

2019.

3

2-build_

01

8_

20190304100745

20200325075220.zip
TE0720-test_board

_noprebuilt

-vivado_

2018

2019.

3

2-build_

01

8_

20190304100755

20200325075301.zip

John Hartfiel

update for -1CR version only (256MB DDR3)

2019-02-21

script update
2020-01-22	2019.2

2018.3

TE0720-test_board-vivado_

2018

2019.

3

2-build_

01

3_

20190221125123

20200122154933.zip
TE0720-test_board_noprebuilt-vivado_

2018

2019.

3

2-build_

01

3_

20190221125133

20200122154951.zip

John Hartfiel

TE Script

script update

rework of the FSBLs

some additional Linux features

for linux user
2020-01-14	2019

2018-08-232018

.2

te0720

TE0720-test_board-vivado_

2018

2019.2-build_

03

3_

20180823185142

20200114090828.zip

te0720

TE0720-test_board_noprebuilt-vivado_

2018

2019.2-build_

03

3_

20180823185158

20200114090837.zip

John Hartfiel

DDR setup bugfix for l1if only

2018-08-132018.2

Vitis script updates (include linux domain and prebuilt linux files for vitis) prebuilt binary export on selection guide
2019-12-18	2019.2	TE0720

te0720

-test_board-vivado_

2018

2019.2-build_

02

1_

20180810162024

20191218151902.zip

te0720

TE0720-test_board_noprebuilt-vivado_

2018

2019.2-build_

02

1_

20180810162040

20191218152732.zip

John Hartfiel

2018

2019.2 update

Board Part Files rework

2018

Vitis support

2019-03-04

-26

2017

2018.

4

3

te0720

TE0720-test_board-vivado_

2017

2018.

4

3-build_

07

01_

20180426144351

20190304100745.zip

te0720

TE0720-test_board_noprebuilt-vivado_

2017

2018.

4

3-build_

07

01_

20180426144405

20190304100755.zip

John Hartfiel

new assembly variant

2018-03-122017.4

update for -1CR version only (256MB DDR3)
2019-02-21	2018.3	TE0720

te0720

-test_board

_noprebuilt

-vivado_

2017

2018.

4

3-build_

06

01_

20180312152408

20190221125123.zip

te0720

TE0720-test_board_noprebuilt-vivado_

2017

2018.

4

3-build_

06

01_

20180312152419

20190221125133.zip

John Hartfiel

TE Script update
rework of the FSBLs
some additional Linux features

add assembly variant

script update

2018-

01

08-

09

23

2017

2018.

4

2	te0720-test_board

_noprebuilt

-vivado_

2017

2018.

4

2-build_

02

03_

20180109121313

20180823185142.zip
te0720-test_board_noprebuilt-vivado_

2017

2018.

4

2-build_

02

03_

20180109121300

20180823185158.zip

John Hartfiel

no design changes
set EEPROM MAC with FSBL+u-boot
FSBL for QSPI Programming

DDR setup bugfix for l1if only
2018-08-13	2018.2	te0720-test_board-vivado_2018.2-build_02_20180810162024.zip te0720-test_board_noprebuilt-vivado_2018.2-build_02_20180810162040.zip	John Hartfiel	2018.2 update Board Part Files rework
2018-04-26	2017.4

2017-11-272017.2

te0720-test_board

_noprebuilt

-vivado_2017.

2

4-build_

05

07_

20171127153028

20180426144351.zip
te0720-test_board_noprebuilt-vivado_2017.

2

4-build_

05

07_

20171127153006

20180426144405.zip

John Hartfiel

remove duplicated content

new assembly variant

2018-03-12

2017-11-20

2017.

2

4	te0720-test_board_noprebuilt-vivado_2017.

2

4-build_

05

06_

20171122074701

20180312152408.zip
te0720-test_board-vivado_2017.

2

4-build_

05

06_

20171122074646

20180312152419.zip

John Hartfiel

initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title-alignment	center
title	Known Issues

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueIssuesDescriptionWorkaroundTo be fixed versionQSPI FlashProgramming QSPI fails with Vivado 2021.2use Vivado 2020.2 or 2019.2 for programming

TE0720-test_board_noprebuilt-vivado_2020.2-build_2_20210217064925.zip

TE0720-test_board-vivado_2020.2-build_2_20210217064913.zip

Linux binaries are missing
boot.scr are only prepared for SD Bootcreate and modify by yourself or use 2019.2 designsolved with 2020-04-01 updateVariant with 256MB DDR only(TE0720-03-1CR)wrong netboot offsetrecreate u-boot on petalinux with reduced netboot offset onlysolved with 2019-03-04 update

add assembly variant script update
2018-01-09	2017.4	te0720-test_board_noprebuilt-vivado_2017.4-build_02_20180109121313.zip te0720-test_board-vivado_2017.4-build_02_20180109121300.zip	John Hartfiel	no design changes set EEPROM MAC with FSBL+u-boot FSBL for QSPI Programming
2017-11-27	2017.2	te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip te0720-test_board-vivado_2017.2-build_05_20171127153006.zip	John Hartfiel	remove duplicated content
2017-11-20	2017.2	te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip te0720-test_board-vivado_2017.2-build_05_20171122074646.zip	John Hartfiel	initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title-alignment	center
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Issues

Description

Workaround

To be fixed version

QSPI Flash

Programming QSPI fails with Vivado 2021.2

use Vivado 2020.2 or 2019.2 for programming

TE0720-test_board_noprebuilt-vivado_2020.2-build_2_20210217064925.zip

TE0720-test_board-vivado_2020.2-build_2_20210217064913.zip

Linux binaries are missing
boot.scr are only prepared for SD Boot

create and modify by yourself or use 2019.2 design

solved with 2020-04-01 update

Variant with 256MB DDR only(TE0720-03-1CR)

wrong netboot offset

recreate u-boot on petalinux with reduced netboot offset only

solved with 2019-03-04 update

Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title-alignment	center
title	Software

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Software	Version	Note
Vitis	2023.2	needed, Vivado is included into Vitis installation
PetaLinux	2023.2	needed

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of hardware which was used to generate the design
mark the module and carrier board, which was used tested with an ^*

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Expand

title	Expand List

Scroll Title

anchor	Table_HWM
title-alignment	center
title	Hardware Modules

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	EMMC	Others	Notes
TE0720-03-1CF^*	1cf_1gb	REV03\|REV02	1GB	32MB	4GB	NA	NA
TE0720-03-14S-1C	14s_1gb	REV03\|REV02	1GB	32MB	4GB	NA	NA
TE0720-03-1CFA	1cf_1gb	REV03\|REV02	1GB	32MB	8GB	NA	NA
TE0720-03-1CR	1cr_256mb	REV03\|REV02	256MB	32MB	NA	NA	NA
TE0720-03-1QF	1qf_1gb	REV03\|REV02	1GB	32MB	4GB	NA	NA
TE0720-03-1QFA	1qf_1gb	REV03\|REV02	1GB	32MB	4GB	NA	NA
TE0720-03-1QFL	1qf_1gb	REV03\|REV02	1GB	32MB	4GB	2.5 mm connectors	low profile
TE0720-03-1QFY	1qf_1gb	REV03	1GB	32MB	4GB	NA	no RTC
TE0720-03-2IF	2if_1gb	REV03\|REV02	1GB	32MB	4GB	NA	NA
TE0720-03-2IFA	2if_1gb	REV03\|REV02	1GB	32MB	4GB	NA	NA
TE0720-03-2IFC3	2if_1gb	REV03\|REV02	1GB	32MB	4GB	2.5 mm connectors	low profile
TE0720-03-2IFC8	2if_1gb	REV03\|REV02	1GB	32MB	32GB	NA	NA
TE0720-03-31C33FA	14s_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-31C33MA	14s_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61C33FA	1cf_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61C33MA	1cf_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61C33MAS	1cf_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61C33MAY	1cf_1gb	REV03	1GB	32MB	8GB	NA	no RTC
TE0720-03-61C530A	1cr_256mb	REV03	256MB	32MB	NA	NA	NA
TE0720-03-61Q33FA	1qf_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61Q33FAE	1qf_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61Q33FL	1qf_1gb	REV03	1GB	32MB	8GB	2.5 mm connectors	low profile
TE0720-03-61Q33MA	1qf_1gb	REV03	1GB	32MB	8GB	NA	NA
TE0720-03-61Q33MAY	1qf_1gb	REV03	1GB	32MB	8GB	NA	no RTC
TE0720-03-61Q33ML	1qf_1gb	REV03	1GB	32MB	8GB	2.5 mm connectors	low profile
TE0720-03-61Q42GA	1qf_256mb	REV03	256MB	32MB	32GB	NA	NA
TE0720-03-61Q42GAY	1qf_256mb	REV03	256MB	32MB	32GB	NA	no RTC
TE0720-03-61Q43FA	1qf_256mb	REV03	256MB	32MB	8GB	NA	NA
TE0720-03-61Q43GA	1qf_256mb	REV03	256MB	32MB	32GB	NA	NA
TE0720-03-61Q43MA	1qf_256mb	REV03	256MB	32MB	8GB	NA	automotive Zynq and DDR
TE0720-03-61Q86KL	1qf_1gb	REV03	1GB	32MB	8GB	NA	Automotive DDR and QSPI
TE0720-03-62I12GA	2if_1gb	REV03	1GB	32MB	32GB	NA	NA
TE0720-03-62I320M	2if_1gb	REV03	1GB	32MB	NA	NA	CAO: no Eth, USB, RTC, VBAT, CryptoKey
TE0720-03-62I33-V1	2if_1gb	REV03	1GB	32MB	NA	NA	NA
TE0720-03-62I330M	2if_1gb	REV03	1GB	32MB	NA	NA	CAO: no Eth, USB, RTC, VBAT, CryptoKey
TE0720-03-62I33FA	2if_1gb	REV03	1GB	32MB	8GB

Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title-alignment	center
title	Software

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueSoftwareVersionNoteVitis2021.2

needed, Vivado is included into Vitis installation

PetaLinux2021.2needed

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of hardware which was used to generate the design
mark the module and carrier board, which was used tested with an ^*

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

4GB

Scroll Title

anchor	Table_HWM
title-alignment	center
title	Hardware Modules

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

Module Model

Board Part Short Name

PCB Revision Support

DDR

QSPI Flash

EMMC

Others

Notes

TE0720-03-2IF

2if_1gb

REV03|REV02

1GB

32MB

	NA	NA
TE0720-03-

2IFC3

62I33FL

2if_1gb

REV03

|REV02

1GB

32MB

4GB

8GB

2.5 mm

connectorslow profile

connectors	low profile
TE0720-03-62I33GA	2if_1gb	REV03	1GB	32MB	32GB	NA	NA
TE0720-03-

2IFC8

62I33MA

2if_1gb

REV03

|REV02

1GB

32MB

32GB

8GB	NA	NA
TE0720-03-

1QF

62I33MAN

1qf

2if_1gb

REV03

|REV02

1GB

32MB

4GB

8GB	NA	NA
TE0720-03-

1CF*

62I33MAY

1cf

2if_1gb

REV03

|REV02

1GB

32MB

4GB

8GB

NA

no RTC

TE0720-03-

1CFA

62I33ML

1cf

2if_1gb

REV03

|REV02

1GB

32MB

8GB

NA

2.5 mm connectors

low profile

NA

TE0720-03-

1CR

62I33NA

1cr

2if_

256mb

1gb

REV03

|REV02

256MB

1GB

32MB

NA

32GB	NA	NA
TE0720-03-

L1IF

64I63FA

l1if_512mb

REV03

|REV02

512MB

32MB

4GB

8GB	NA	LP DDR3
TE0720-03-

14S-1C

L1IF

14s

l1if_

1gb

512mb

REV03|REV02

1GB

512MB

32MB

4GB

NA

LP DDR3

TE0720-03-

1QFA

S006C1

1qf_1gb

REV03

|REV02

1GB

32MB

4GB

8GB

NA

CAO

TE0720-03-

2IFA

S007C1

2if

1qf_1gb

REV03

|REV02

1GB

32MB

4GB

8GB

NA

CAO

TE0720-03-

1QFL

S008C1

1qf_1gb

REV03

|REV02

1GB

32MB

4GB2.5 mm connectors

8GB

NA

CAO

low profile

TE0720-03-

31C33FA

S009C1

14s

1qf_1gb

REV03

1GB

32MB

8GB

NA

CAO

TE0720-03-

61C33FA

S010

1cf

1qf_1gb

REV03

1GB

32MB

8GB

NA

CAO

TE0720-03-

61C530A

S011

1cr

2if_

256mb

1gb

REV03

256MB

1GB

32MB

NA

8GB

NA

CAO: no ETH

TE0720-03-

61Q33FA

S012

1qf

2if_1gb

REV03

1GB

32MB

8GB

NA

CAO

TE0720-03-

61Q33FL

S013

1qf

1cf_1gb

REV03

1GB

32MB

8GB

2.5 mm connectors

NA

CAO

low profile

TE0720-03-

61Q42GA

S014

1qf

2if_

256mb

1gb

REV03

256MB

1GB

32MB

32GB

8GB

NA

CAO

TE0720-03-

61Q43FA

S016

1qf

1cr_256mb

REV03

256MB

32MB

8GB

NA

CAO: no RTC

TE0720-03-

61Q43GA

S017

1qf

2if_

256mb

1gb

REV03

256MB

1GB

32MB

32GB

8GB

NA

CAO: no RTC

TE0720-03-

61Q86KL

S020

1qf

2if_1gb

REV03

1GB

32MB

8GB

NA

Automotive DDR and QSPI

CAO

TE0720-03-

62I33GA

S032

2if_1gb

REV03

1GB

32MB

32GB

8GB

NA

CAO

TE0720-

03

04-

62I12GA

31C33MA

2if

14s_1gb

REV03

REV04

1GB

32MB

32GB

8GB	NA	NA
TE0720-

03

04-

62I320M

61C33MA

2if

1cf_1gb

REV03

REV04

1GB

32MB

NA

8GB

NA

CAO: no Eth USB RTC VBAT CryptoKey

	NA
TE0720-

03

04-

62I330M

61C530A

2if

1cr_

1gb

256mb

REV03

REV04

1GB

256MB

32MB

NA

CAO: no Eth USB RTC VBAT CryptoKey

NA

TE0720-

03

04-

62I33FA

61Q33MA

2if

1qf_1gb

REV03

REV04	1GB	32MB	8GB	NA	NA
TE0720-

03

04-

62I33FL

61Q33ML

2if

1qf_1gb

REV03

REV04	1GB	32MB	8GB	2.5 mm connectors	low profile
TE0720-

03

04-

64I63FA

61Q43MA

l1if

1qf_

512mb

256mb

REV03

REV04

512MB

256MB

32MB

8GB

NA

LP DDR3

automotive Zynq and DDR

TE0720-

03

04-

1QFY

61Q86PL

1qf_1gb

REV03

REV04

1GB

32MB

4GB

8GB

NA

no RTC

Automotive DDR and QSPI

TE0720-

03

04-

31C33MA

62I33MA

14s

2if_1gb

REV03

REV04	1GB	32MB	8GB	NA	NA
TE0720-

03

04-

61C33MAS

62I33MAN

1cf

2if_1gb

REV03

REV04	1GB	32MB	8GB	NA	NA
TE0720-

03-61Q33MA1qf

04-62I33ML	2if_1gb	REV04	1GB	32MB	8GB	2.5 mm connectors	low profile
TE0720-04-62I33NA	2if_1gb

REV03

REV04

1GB

32MB

8GB

32GB	NA	NA
TE0720-

03

04-

61Q33MAY

64I63MA

1qf

l1if_

1gb

512mb

REV03

REV04

1GB

512MB

32MB

8GB

NA

no RTC

LP DDR3

TE0720-

03

04-

61Q33ML

S001C1

1qf_1gb

REV03

REV04

1GB

32MB

8GB

2.5 mm connectors

NA

CAO

low profile

TE0720-

03

04-

61Q42GAY

S007C1

1qf_

256mb

1gb

REV03

REV04

256MB

1GB

32MB

32GB

8GB

NA

no RTC

CAO

TE0720-

03

04-

61Q43MA

S016

1qf

2if_

256mb

1gb

REV03

REV04

256MB

1GB

32MB

8GB

NA

automotive Zynq mit IME1G16D3EEBG-15:EI

CAO

TE0720-

03

04-

62I33MA

S019

2if

1cf_1gb

REV03

REV04

1GB

32MB

8GB

NA

CAO

TE0720-

03

04-

62I33MAN

S022

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

industrieller Temperaturbereich; coated

CAO

TE0720-

03

04-

62I33MAY

S023

2if_1gb

REV03

1GB

32MB

8GB

NA

no RTC

CAO

TE0720-

03

04-

62I33ML

S025

2if_1gb

REV03

REV04

1GB

32MB

8GB

2.5 mm connectors

NA

CAO

low profile

TE0720-

03

04-

62I33NA

S026

2if

2ef_1gb

REV03

REV04

1GB

32MB

32GB

8GB

NA

CAO

TE0720-

03

04-

S006C1

S027

1qf

2if_1gb

REV03

REV04

1GB

32MB

8GB

NAcustom variant

2.5 mm connectors	CAO and low profile
TE0720-

03

04-

S007C1

S028

1qf

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

custom variant

CAO

TE0720-

03

04-

S011

S029

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

custom variant, no ETH

CAO

TE0720-

03

04-

S012

S030

2if_1gb

REV03

REV04

1GB

32MB

8GB

32GB

NA

custom variant

CAO

TE0720-

03

04-

S014

S031

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

custom variant

CAO

TE0720-

03

04-

S016

S032

1cr

1qf_

256mb

1gb

REV03

REV04

256MB

1GB

32MB

NA

8GB

NA

custom variant, no RTC

CAO

TE0720-

03

04-

S017

S033

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

custom variant, no RTC

CAO

TE0720-

03

04-

61C33MA

S034

1cf

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

CAO

TE0720-

03

04-

61C33MAY

S035

1cf_1gb

REV03

REV04

1GB

32MB

8GB

NA

no RTC

CAO

TE0720-

03

04-

62I33-V1

S036

2if_1gb

REV03

REV04

1GB

32MB

NA

8GB

NA

CAO

TE0720-

03

04-

S013

S037

1cf

2if_1gb

REV03

REV04

1GB

32MB

8GB

NA

custom variant

CAO

^*used as reference

Design supports following carriers:

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title	Hardware Carrier

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Carrier Model	Notes
TE0701	See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
TE0703*	See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers Used as reference carrier.
TE0705	See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
TE0706*	See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
TEBA0841	See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers No SD Slot available, pins goes to Pin Header For TEBA0841 REV01, please contact TE support

^*used as reference

Additional HW Requirements:

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title	Additional Hardware

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Additional Hardware	Notes
USB Cable for JTAG/UART	Check Carrier Board and Programmer for correct type
XMOD Programmer	Carrier Board dependent, only if carrier has no own FTDI

Content

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Notes :

content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices

Design Sources

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Type	Location	Notes
Vivado	<project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files	Vivado Project will be generated by TE Scripts
Vitis	<project folder>\sw_lib	Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux	<project folder>\os\petalinux	PetaLinux template with current configuration

Additional Sources

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title	Additional design sources

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Type	Location	Notes
init.sh	<project folder>\misc\sd\	Additional Initialization Script for Linux

Prebuilt

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Notes :

prebuilt files

Template Table:

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Device Tree	*.dts	Device tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Device Tree	*.dts	Device tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0720 "Test Board" Reference Design

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

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Note:

Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select create and open delivery binary folder
  Info
  Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block
language py
theme Midnight
title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0720 (optional)
Note
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.

SD-Boot mode

Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)

Select SD Card as Boot Mode (or QSPI - depending on step 1)

Info
Note: See TRM of the Carrier, which is used.

Tip

Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr

Power On PCB

Expand

title	boot process

1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

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This step depends on Xilinx Device/Hardware

for Zynq-7000 series

1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

for ZynqMP

1. ZynqMP Boot ROM FSBL from QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

for Microblaze with Linux

1. FPGA Loads Bitfile from Flash,

2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

4. U-boot loads Linux from QSPI Flash into DDR

for native FPGA

...

Linux

Open Serial Console (e.g. putty)
- Speed: 115200
- select COM Port
  Info
  Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block
language bash
theme Midnight
theme Midnight
title (can be skipped with config auto login in petalinux)
# password disabled petalinux login: root Password: root
Info
Note: Wait until Linux boot finished

You can use Linux shell now.

Code Block

language	bash
theme	Midnight

i2cdetect -y -r 0	(check I2C 0 Bus)
i2cdetect -y -r 1	(check I2C 1 Bus)
dmesg | grep rtc	(RTC check)
udhcpc				(ETH0 check)
lsusb				(USB check)

Option Features
- Webserver to get access to Zynq
  - insert IP on web browser to start web interface
- init.sh scripts
  - add init.sh script on SD, content will be load automatically on startup (template is included in "<project folder>\misc\SD")

Vivado HW Manager

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Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
- SI5338 CLKs:
  - Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz
  - expected CLK Frequency...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

Monitoring: PHY LED
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title	Vivado Hardware Manager

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System Design - Vivado

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Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Figure_BD

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PS Interfaces

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Note:

optional for Zynq / ZynqMP only
add basic PS configuration

Activated interfaces:

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Type	Note
DDR	---
QSPI	MIO
SD0	MIO
SD1	MIO
I2C0	MIO
I2C1	EMIO
UART0	MIO
UART1	MIO
GPIO	MIO
SWDT	EMIO
TTC0..1	EMIO
ETH0	MIO
USB0	MIO

Constrains

Constraints

Basic module

constrains

constraints

Code Block

language	ruby
title	_i_bitgen_common.xdc

#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Code Block

language	ruby
title	_i_common.xdc

#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific

constrain

constraints

Code Block

language	ruby
title	_i_TE0720-SC.xdc

#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16]

Software Design - Vitis

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Note:

optional chapter separate
sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

----------------------------------------------------------FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 20212023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 20212023.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 20212023.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 20212023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

- Si5338 Configuration
- ETH+OTG Reset over MIO
Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

fsbl

TE modified 20212023.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
- USB PHY Reset
- Configure LED usage

fsbl_flash

TE modified 2021.2 FSBL

General:

- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
- USB PHY Reset
- Configure LED usage
Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

hello_te0720

Hello TE0720 is a Xilinx Hello World App in Endless loopexample as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design - PetaLinux

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Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_0_SELECT=y
# CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_1_SELECT is not set
CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="ps7_uart_0"
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000
add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM
_UBOOT_EXT_DTB=y
- _FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0x0100000
- CONFIG_
UBOOT
- SUBSYSTEM_
EXT
- FLASH_
DTB
- PS7_
FROM_DTS=""CONFIG_UBOOT_DTB_PACKAGE_NAME="u-boot.dtb"
- QSPI_0_BANKLESS_PART1_SIZE=0x1400000
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=
0x01400000
- 0x0020000
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE
=0x40000
- =0x40000
Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_
FLASH_PS7_QSPI_0_BANKLESS_PART4_NAME
- PRODUCT="
spare
- TE0720"

Note: for variants with 256MB DDR only, change NET Boot Address to 0x8000000 on boot.src file

U-Boot

Start with petalinux-config -c u-boot

Changes:

MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE
CONFIG_QSPI_BOOT=y
CONFIG_SD_BOOT=y
CONFIG_ENV_IS_NOWHERE
- =y
- CONFIG_
ENV_OVERWRITE=y (used to overwrite default mac address and use from EEPROM)
CONFIG_ENV_IS_IN_FAT=y (needed to boot from SD card)
CONFIG_ENV_IS_IN_SPI_FLASH=y (needed to boot from QSPI flash)
- PREBOOT="echo U-BOOT for petalinux;echo Importing env from FSBL shared area at 0xFFFFFC00;if test *0xFFFFFC00 == 0xCAFEBABE;then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo;"
Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
# CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_BOOT_SCRIPT_OFFSET=
0x1920000
- 0x1520000
  (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)
Identification
- CONFIG_IDENT_
PREBOOT=echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo;
- STRING=" TE0720"

Device Tree

Code Block

language	js
title	Device Tree (system-user.dtsi in device-tree and uboot-device-tree)

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};
  
 
/* bugfix */
/* Uncomment on usage with single core variant only */
/*
&amba {
	    ptm@f889d000 {
		        cpu = <&cpu0>;
	    };
};
*/
 
 
/* default */
   
/*------------------ QSPI PHY --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        
        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <90000000>;
    };
};

  
  
/*-------------------- ETH PHY ----------------*/
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
        };
    };
};
   
 
/*-------------------- USB PHY ----------------*/  
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
   
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};
   
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
   
    iexp@20 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x20>;
        gpio-controller;
    };
   
    iexp@21 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x21>;
        gpio-controller;
    };
   
    /* Commend out if no RTC is fitted */
    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;
    };
};

FSBL patch

Device Tree patch (for single core variant)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\device-tree\files\"Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

CONFIG_RTC_DRV_ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

For web server app:
- CONFIG_
i2c
- busybox-
tools
- httpd=y
For additional test tools only:
- CONFIG_
busybox
- i2c-
httpd=y (for web server app)
- tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- CONFIG_util-linux-umount=y
- CONFIG_util-linux-mount=y
For usage of phytool:
- CONFIG_ethtool=
y (for usage of phytool)
- y

For auto login:#

CONFIG_auto-login

is not set

=y

Add in "<project folder>\os\petalinux\project-spec\meta-user\conf\petalinuxbsp.conf:"

Code Block

language	js

IMAGE_INSTALL_:append += "\
phytool \
"

FSBL patch (alternative for vitis fsbl trenz patch)

See "

\ phytool \

<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

No additional software is needed.

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
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Date

Document Revision

Authors

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat

Page info

	modified-user
	modified-user

Device-Tree patch for single core variants

2024-01-22

v.58

Manuela Strücker

2023.2 release

2023-07-19

v.57

Waldemar Hanemann

bugfix -boot up on first power up only. qspi x4 - device tree node entry

2023-07-19

v.56

Waldemar Hanemann

2022.2 release

2022-05-09

v.52

Thomas Dück

bugfix os folder
bugfix table of content

2022-01-25

v.50

Manuela Strücker

2021.2 release

2021-12-16

v.49

Manuela Strücker

new assembly variants

2021-11-29

v.46

John Hartfiel

new assembly variants

2021-07-19

v.45

Manuela Strücker

boot.scr file updated for 256 MB QSPI flash size variants

2021-05-25

v.44

Manuela Strücker

update board files
update boot.scr file

2021-04-01

v.42

John Hartfiel

Design update

2021-02-26

v.41

John Hartfiel

add issue notes

2021-02-17

v.40

John Hartfiel

2020.2 release

2020-03-25

v.39

John Hartfiel

script update

2020-01-22

v.38

John Hartfiel

script update for linux user

2020-01-14

v.37

John Hartfiel

Vitis script updates (include linux domain and prebuilt linux files for vitis)
prebuilt binary export on selection guide

2019-12-19

v.36

John Hartfiel

2019.2 release

2019-12-03

v.34

John Hartfiel

bugfix document link

2019-10-28

v.33

John Hartfiel

removed remove instructions that are no longer used

2019-05-07

v.31

John Hartfiel

Some FSBL notes
wrong link

2019-03-06

v.28

John Hartfiel

Fixed prebuilt issue for TE0720-03-1CR

2019-03-01

v.27

John Hartfiel

Known issue for TE0720-03-1CR linux design

2019-02-21

v.26

John Hartfiel

2018.3 release finished (include design reworks)

2018-08-30

v.25

John Hartfiel

update documentation PS configuration

2018-08-23

v.24

John Hartfiel

update l1if board parts

2018-08-13

v.23

John Hartfiel

2018.4 release

2018-04-26

v.22

John Hartfiel

add assembly variant

2018-02-20

v.20

John Hartfiel

small documentation update

2018-01-09

v.16

John Hartfiel

Release 2017.4
Documentation update

2017-11-27

v.14

John Hartfiel

Typo correction
Design Files update

2017-11-22

v.12

John Hartfiel

Update HW list

2017-11-22

v.11

John Hartfiel

Release 2017.2

2017-11-20

v.1

Page info

	created-user
	created-user

Initial release

--

All

Page info

	modified-users
	modified-users

--

Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 51

New Version Current

Key

Overview

Key Features

Revision History

Release Notes and Know Issues

Release Notes and Know Issues

Requirements

Software

Hardware

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI-Boot mode

SD-Boot mode

JTAG

Usage

Linux

Vivado HW Manager

System Design - Vivado

Block Design

PS Interfaces

Constraints

Basic module

constraints

Design specific

constraints

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

fsbl

fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

fsbl

fsbl_flash

hello_te0720

u-boot

Software Design - PetaLinux

Config

U-Boot

Device Tree

FSBL patch

Device Tree patch (for single core variant)

Kernel

Rootfs

FSBL patch (alternative for vitis fsbl trenz patch)

Applications

startup

webfwu

Additional Software

Appx. A: Change History and Legal Notices

Document Change History

Legal Notices

Table of contents