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  • This line was added.
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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
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        ExampleComment
        12



  • ...

Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


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Notes :

Zynq PS Design with Linux Example and PHY status LED on Vivado HW-Manager.

Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2021.2
  • PetaLinux
  • SD
  • ETH (use EEPROM MAC)
  • USB
  • I2C
  • RTC
  • VIO PHY LED
  • FSBL for EEPROM MAC and CPLD access / petalinux patch
  • Special FSBL for QSPI Programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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DateVivadoProject BuiltAuthorsDescription
2022-02-022021.2TE0720-test_board-vivado_2021.2-build_11_20220202131818.zip
TE0720-test_board_noprebuilt-vivado_2021.2-build_11_20220202131838.zip
Manuela Strücker
  • bugfix "os" folder
  • updated Petalinux config
    • added QSPI Partition for bootscr file
2022-01-252021.2TE0720-test_board-vivado_2021.2-build_10_20220125090947.zip
TE0720-test_board_noprebuilt-vivado_2021.2-build_10_20220125090947.zip
Manuela Strücker
  • 2021.2 update
2021-12-152020.2TE0720-test_board-vivado_2020.2-build_9_20211215123235.zip
TE0720-test_board-vivado_2020.2-build_9_20211215123235_production.zip
Manuela Strücker
  • new Assembly variants
2021-11-292020.2TE0720-test_board-vivado_2020.2-build_9_20211129062154.zip
TE0720-test_board_noprebuilt-vivado_2020.2-build_9_20211129062716.zip
Manuela Strücker
  • new Assembly variants
2021-07-192020.2TE0720-test_board_noprebuilt-vivado_2020.2-build_6_20210719131800.zip
TE0720-test_board-vivado_2020.2-build_6_20210719131744.zip
Manuela Strücker
  • boot.scr file updated for 256 MB QSPI flash size variants
2021-04-302020.2TE0720-test_board_noprebuilt-vivado_2020.2-build_5_20210430085624.zip
TE0720-test_board-vivado_2020.2-build_5_20210430085609.zip
Manuela Strücker
  • update board files
  • update boot.scr file
2021-04-012020.2TE0720-test_board_noprebuilt-vivado_2020.2-build_4_20210401140444.zip
TE0720-test_board-vivado_2020.2-build_4_20210401140432.zip
John Hartfiel
  • bugfix missing binaries+ boot.scr file(supports now QSPI and SD boot with image.ub on SD)
2021-02-172020.2TE0720-test_board_noprebuilt-vivado_2020.2-build_2_20210217064925.zip
TE0720-test_board-vivado_2020.2-build_2_20210217064913.zip
John Hartfiel
  • 2020.2 update
  • add boot.scr file
  • petalinux fsbl patch (beta-version)
2020-03-252019.2TE0720-test_board_noprebuilt-vivado_2019.2-build_8_20200325075220.zip
TE0720-test_board-vivado_2019.2-build_8_20200325075301.zip
John Hartfiel
  • script update
2020-01-222019.2TE0720-test_board-vivado_2019.2-build_3_20200122154933.zip
TE0720-test_board_noprebuilt-vivado_2019.2-build_3_20200122154951.zip
John Hartfiel
  • script update for linux user
2020-01-142019.2TE0720-test_board-vivado_2019.2-build_3_20200114090828.zip
TE0720-test_board_noprebuilt-vivado_2019.2-build_3_20200114090837.zip
John Hartfiel
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
2019-12-182019.2TE0720-test_board-vivado_2019.2-build_1_20191218151902.zip
TE0720-test_board_noprebuilt-vivado_2019.2-build_1_20191218152732.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
2019-03-042018.3TE0720-test_board-vivado_2018.3-build_01_20190304100745.zip
TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190304100755.zip
John Hartfiel
  • update for -1CR version only (256MB DDR3)
2019-02-212018.3TE0720-test_board-vivado_2018.3-build_01_20190221125123.zip
TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190221125133.zip
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
2018-08-232018.2

te0720-test_board-vivado_2018.2-build_03_20180823185142.zip
te0720-test_board_noprebuilt-vivado_2018.2-build_03_20180823185158.zip

John Hartfiel
  • DDR setup bugfix for l1if only
2018-08-132018.2te0720-test_board-vivado_2018.2-build_02_20180810162024.zip
te0720-test_board_noprebuilt-vivado_2018.2-build_02_20180810162040.zip
John Hartfiel
  • 2018.2 update
  • Board Part Files rework
2018-04-262017.4te0720-test_board-vivado_2017.4-build_07_20180426144351.zip
te0720-test_board_noprebuilt-vivado_2017.4-build_07_20180426144405.zip
John Hartfiel
  • new assembly variant
2018-03-122017.4te0720-test_board_noprebuilt-vivado_2017.4-build_06_20180312152408.zip
te0720-test_board-vivado_2017.4-build_06_20180312152419.zip
John Hartfiel
  • add assembly variant
  • script update
2018-01-092017.4te0720-test_board_noprebuilt-vivado_2017.4-build_02_20180109121313.zip
te0720-test_board-vivado_2017.4-build_02_20180109121300.zip
John Hartfiel
  • no design changes
  • set EEPROM MAC with FSBL+u-boot
  • FSBL for QSPI Programming
2017-11-272017.2te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip
te0720-test_board-vivado_2017.2-build_05_20171127153006.zip
John Hartfiel
  • remove duplicated content
2017-11-202017.2te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip
te0720-test_board-vivado_2017.2-build_05_20171122074646.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed


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IssuesDescriptionWorkaroundTo be fixed version
QSPI FlashProgramming QSPI fails with Vivado 2021.2use Vivado 2020.2 or 2019.2 for programming

TE0720-test_board_noprebuilt-vivado_2020.2-build_2_20210217064925.zip

TE0720-test_board-vivado_2020.2-build_2_20210217064913.zip

Linux binaries are missing
boot.scr are only prepared for SD Boot
create and modify by yourself or use 2019.2 designsolved with 2020-04-01 update
Variant with 256MB DDR only(TE0720-03-1CR)wrong netboot offsetrecreate u-boot on petalinux with reduced netboot offset onlysolved with 2019-03-04 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Vitis2021.2

needed, Vivado is included into Vitis installation

PetaLinux2021.2needed


Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *
Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0720-03-2IF2if_1gbREV03|REV021GB32MB4GBNANA
TE0720-03-2IFC32if_1gbREV03|REV021GB32MB4GB2.5 mm connectorslow profile
TE0720-03-2IFC82if_1gbREV03|REV021GB32MB32GBNANA
TE0720-03-1QF1qf_1gbREV03|REV021GB32MB4GBNANA
TE0720-03-1CF*1cf_1gbREV03|REV021GB32MB4GBNANA
TE0720-03-1CFA1cf_1gbREV03|REV021GB32MB8GBNANA
TE0720-03-1CR1cr_256mbREV03|REV02256MB32MBNANANA
TE0720-03-L1IFl1if_512mbREV03|REV02512MB32MB4GBNALP DDR3
TE0720-03-14S-1C14s_1gbREV03|REV021GB32MB4GBNANA
TE0720-03-1QFA1qf_1gbREV03|REV021GB32MB4GBNANA
TE0720-03-2IFA2if_1gbREV03|REV021GB32MB4GBNANA
TE0720-03-1QFL1qf_1gbREV03|REV021GB32MB4GB2.5 mm connectorslow profile
TE0720-03-31C33FA14s_1gbREV031GB32MB8GBNANA
TE0720-03-61C33FA1cf_1gbREV031GB32MB8GBNANA
TE0720-03-61C530A1cr_256mbREV03256MB32MBNANANA
TE0720-03-61Q33FA1qf_1gbREV031GB32MB8GBNANA
TE0720-03-61Q33FL1qf_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-61Q42GA1qf_256mbREV03256MB32MB32GBNANA
TE0720-03-61Q43FA1qf_256mbREV03256MB32MB8GBNANA
TE0720-03-61Q43GA1qf_256mbREV03256MB32MB32GBNANA
TE0720-03-61Q86KL1qf_1gbREV031GB32MB8GBNAAutomotive DDR and QSPI
TE0720-03-62I33GA2if_1gbREV031GB32MB32GBNANA
TE0720-03-62I12GA2if_1gbREV031GB32MB32GBNANA
TE0720-03-62I320M2if_1gbREV031GB32MBNANACAO: no Eth USB RTC VBAT CryptoKey
TE0720-03-62I330M2if_1gbREV031GB32MBNANACAO: no Eth USB RTC VBAT CryptoKey
TE0720-03-62I33FA2if_1gbREV031GB32MB8GBNANA
TE0720-03-62I33FL2if_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-64I63FAl1if_512mbREV03512MB32MB8GBNALP DDR3
TE0720-03-1QFY1qf_1gbREV031GB32MB4GBNAno RTC
TE0720-03-31C33MA14s_1gbREV031GB32MB8GBNANA
TE0720-03-61C33MAS1cf_1gbREV031GB32MB8GBNANA
TE0720-03-61Q33MA1qf_1gbREV031GB32MB8GBNANA
TE0720-03-61Q33MAY1qf_1gbREV031GB32MB8GBNAno RTC
TE0720-03-61Q33ML1qf_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-61Q42GAY1qf_256mbREV03256MB32MB32GBNAno RTC
TE0720-03-61Q43MA1qf_256mbREV03256MB32MB8GBNAautomotive Zynq mit IME1G16D3EEBG-15:EI
TE0720-03-62I33MA2if_1gbREV031GB32MB8GBNANA
TE0720-03-62I33MAN2if_1gbREV031GB32MB8GBNAindustrieller Temperaturbereich; coated
TE0720-03-62I33MAY2if_1gbREV031GB32MB8GBNAno RTC
TE0720-03-62I33ML2if_1gbREV031GB32MB8GB2.5 mm connectorslow profile
TE0720-03-62I33NA2if_1gbREV031GB32MB32GBNANA
TE0720-03-S006C11qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S007C11qf_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0112if_1gbREV031GB32MB8GBNAcustom variant, no ETH
TE0720-03-S0122if_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0142if_1gbREV031GB32MB8GBNAcustom variant
TE0720-03-S0161cr_256mbREV03256MB32MBNANAcustom variant, no RTC
TE0720-03-S0172if_1gbREV031GB32MB8GBNAcustom variant, no RTC
TE0720-03-61C33MA1cf_1gbREV031GB32MB8GBNANA
TE0720-03-61C33MAY1cf_1gbREV031GB32MB8GBNAno RTC
TE0720-03-62I33-V12if_1gbREV031GB32MBNANANA
TE0720-03-S0131cf_1gbREV031GB32MB8GBNAcustom variant

*used as reference

Design supports following carriers:

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Carrier ModelNotes
TE0701
TE0703
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • Used as reference carrier.
TE0705
TE0706*
TEBA0841
  • See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
  • No SD Slot available, pins goes to Pin Header
  • For TEBA0841 REV01, please contact TE support

*used as reference


Additional HW Requirements:

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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI


Content

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Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

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TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration



Additional Sources

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TypeLocationNotes
init.sh<project folder>\misc\sd\Additional Initialization Script for Linux


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems





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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
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    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow


  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    Code Block
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    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      Info

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


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      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ZynqMP

      • copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for Microblaze

      • ...


  8. Generate Programming Files with Vitis

    Code Block
    languagepy
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    titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    Note

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Info

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0720 (optional)


    Note

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.src and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Info

    Note: See TRM of the Carrier, which is used.


    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. Power On PCB

    Expand
    titleboot process

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Page properties
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    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP

    1. ZynqMP Boot ROM FSBL from QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for Microblaze with Linux

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...


Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Info

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Linux Console:

    Code Block
    languagebash
    themeMidnight
    petalinux login: root
    Password: root


    Info

    Note: Wait until Linux boot finished


  3. You can use Linux shell now.

    Code Block
    languagebash
    themeMidnight
    i2cdetect -y -r 0	(check I2C 0 Bus)
    i2cdetect -y -r 1	(check I2C 1 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)


  4. Option Features
    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template is included in "<project folder>\misc\SD") 

Vivado HW Manager 

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequency...
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
  • Monitoring: PHY LED

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titleVivado Hardware Manager

System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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TypeNote
DDR---
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
I2C1EMIO
UART0MIO
UART1MIO
GPIOMIO
SWDTEMIO
TTC0..1EMIO
ETH0MIO
USB0MIO



Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design


Code Block
languageruby
title_i_common.xdc
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

Code Block
languageruby
title_i_TE0720-SC.xdc
#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16]

Software Design - Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2021.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2021.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

fsbl

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY
    • USB PHY Reset
    • Configure LED usage

fsbl_flash

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0720

Hello World App in Endless loop.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
  • CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
  • CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_0_SELECT=y
  • # CONFIG_SUBSYSTEM_FSBL_SERIAL_PS7_UART_1_SELECT is not set
  • CONFIG_SUBSYSTEM_SERIAL_FSBL_IP_NAME="ps7_uart_0"
  • CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x100000
  • CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y

  • CONFIG_UBOOT_EXT_DTB_FROM_DTS=""

  • CONFIG_UBOOT_DTB_PACKAGE_NAME="u-boot.dtb"

  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=0x01400000
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE=0x40000
  • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART4_NAME="spare"

Note: for variants with 256MB DDR only, change NET Boot Address to 0x8000000 on boot.src file

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_NOWHERE=y
  • CONFIG_ENV_OVERWRITE=y                       (used to overwrite default mac address and use from EEPROM)
  • CONFIG_ENV_IS_IN_FAT=y                            (needed to boot from SD card)
  • CONFIG_ENV_IS_IN_SPI_FLASH=y                  (needed to boot from QSPI flash)
  • # CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x1920000   (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)
  • CONFIG_PREBOOT=echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo;



Device Tree


Code Block
languagejs
titleDevice Tree (system-user.dtsi in device-tree and uboot-device-tree)

Code Block
language
js
/include/ "system-conf.dtsi"
/ {
};
 

/* bugfix */
/* Uncomment on usage with single core variant only */
/*
&amba {
	ptm@f889d000 {
		cpu = <&cpu0>;
	};
};
*/ 
 
/* default */
  
/*------------------ QSPI PHY --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
  
  
/*-------------------- ETH PHY ----------------*/
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            compatible = "marvell,88e1510";
            device_type = "ethernet-phy";
            reg = <0>;
        };
    };
};
  

/*-------------------- USB PHY ----------------*/  
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
  
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};
  
/* I2C need I2C1 connected to te0720 system controller ip */
&i2c1 {
  
    iexp@20 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x20>;
        gpio-controller;
    };
  
    iexp@21 {       // GPIO in CPLD
        #gpio-cells = <2>;
        compatible = "ti,pcf8574";
        reg = <0x21>;
        gpio-controller;
    };
  
    /* Commend out if no RTC is fitted */
    rtc@6F {        // Real Time Clock
        compatible = "isl12022";
        reg = <0x6F>;
    };
};  

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_RTC_DRV_ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y                           (for web server app)
  • CONFIG_packagegroup-petalinux-utils=y      (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
  • CONFIG_util-linux-umount=y
  • CONFIG_util-linux-mount=y
  • CONFIG_ethtool=y                                      (for usage of phytool)
  • # CONFIG_auto-login is not set


Add in <project folder>\os\petalinux\project-spec\meta-user\conf\petalinuxbsp.conf:

Code Block
languagejs
IMAGE_INSTALL_append += "\
phytool \
"

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

No additional software is needed.


Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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DateDocument RevisionAuthorsDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

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infoTypeCurrent version
prefixv.
typeFlat

Page info
modified-user
modified-user

  • bugfix os folder
  • bugfix table of content
2022-01-25v.50Manuela Strücker
  • 2021.2 release
2021-12-16v.49Manuela Strücker
  • new assembly variants
2021-11-29v.46John Hartfiel
  • new assembly variants
2021-07-19v.45Manuela Strücker
  • boot.scr file updated for 256 MB QSPI flash size variants
2021-05-25v.44Manuela Strücker
  • update board files
  • update boot.scr file

2021-04-01

v.42

John Hartfiel

  • Design update
2021-02-26v.41John Hartfiel
  • add issue notes
2021-02-17v.40John Hartfiel
  • 2020.2 release
2020-03-25v.39John Hartfiel
  • script update
2020-01-22v.38John Hartfiel
  • script update for linux user
2020-01-14v.37John Hartfiel
  • Vitis script updates (include linux domain and prebuilt linux files for vitis)
  • prebuilt binary export on selection guide
2019-12-19v.36John Hartfiel
  • 2019.2 release
2019-12-03v.34John Hartfiel
  • bugfix document link
2019-10-28v.33John Hartfiel
  • removed remove instructions that are no longer used

2019-05-07

v.31John Hartfiel
  • Some FSBL notes
  • wrong link
2019-03-06v.28John Hartfiel
  • Fixed prebuilt issue for TE0720-03-1CR
2019-03-01v.27John Hartfiel
  • Known issue for TE0720-03-1CR linux design

2019-02-21

v.26John Hartfiel
  • 2018.3 release finished (include design reworks)
2018-08-30v.25John Hartfiel
  • update documentation PS configuration

2018-08-23

v.24

John Hartfiel
  • update l1if board parts

2018-08-13

v.23John Hartfiel
  • 2018.4 release

2018-04-26

v.22John Hartfiel
  • add assembly variant
2018-02-20v.20John Hartfiel
  • small documentation update
2018-01-09v.16John Hartfiel
  • Release 2017.4
  • Documentation update
2017-11-27v.14John Hartfiel
  • Typo correction
  • Design Files update
2017-11-22v.12John Hartfiel
  • Update HW list
2017-11-22

v.11

John Hartfiel
  • Release 2017.2
2017-11-20v.1

Page info
created-user
created-user

  • Initial release
--All

Page info
modified-users
modified-users

--


Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices



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