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The Trenz Electronic TEI0001 MAX1000 is a low cost small-sized FPGA module integrating a Intel Cyclone 10LP 10CL025 MAX 10 FPGA SoC, 2 8 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.


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Refer to for the current online version of this manual and other available documentation.

Key Features

  • Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC

  • 8 MByte SDRAM
  • 2 8 MByte serial configuration QSPI Flash memory

  • ST Microelectronics LIS3DH 3-axis accelerometer
  • JTAG and UART over Micro USB2 connector
  • 1x6 pin header for JTAG access to FPGA SoC
  • 1x PMOD header providing 8 GPIOs
  • 2x 14-pin headers (2,54 mm pitch) providing 23 GPIOs22 GPIOs with 7 analog inputs as alternative function

  • 1x 3-pin header providing 2 GPIOsanalog inputs or 1 GPIO
  • 8x user LEDs

  • 1x user push button
  • 5.0V single power supply with on-board voltage regulators
  • Size: 61.5 x 25 mm


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titleFigure 1: TEI0003-02 block diagram
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diagramNameTEI0001 block diagram

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Main Components

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titleFigure 2: TEI0003-02 FPGA module
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diagramNameTEI0001 main components

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  1. Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC, U1
  2. Winbond W9864G6JT 8 Mbyte SDRAM 166MHz, U2
  3. Intel EPCQ16ASI8N 2 MByte serial configuration 8 Mbyte QSPI Flash memory, U5
  4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
  5. FTDI USB2 to JTAG/UART adapter, U3
  6. Configuration EEPROM for FTDI chip, U9
  7. 12.0000 MHz oscillator, U7
  8. 8x red user LEDs, D2 ... D9
  9. Red LED (Conf. DONE), D10
  10. Green LED (indicating supply voltage), D1
  11. Push button (user), S2
  12. Push button (reset), S1
  13. Micro USB2 B socket (receptacle), J9
  14. 1x14 pin header (2.54mm pitch), J2
  15. 1x6 pin header (2.54mm pitch), J4
  16. 2x6 Pmod connector, J6
  17. 3-pin header (2.54mm pitch), J3
  18. 1x14 pin header (2.54mm pitch), J1


Storage device name



Serial configuration memoryQuad SPI Flash, U5

DEMO Design

I2C Configuration EEPROM, U9



Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memoryThe FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Signals, Interfaces and Pins


2 46 3low active Reset input
BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J2J19 4 I/O's3.3V-
J68 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same bank or pins can be sharedPmod connector
5J18 2 I/O's3.3V-
J3J22 9 I/O's3.3V-5J12 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)-
1A6J68 I/O'sJ17x analog inputs or GPIO's, 1x Analog reference voltage (AREF)3.3VPmod Connector
1J44 I/O's3.3VJTAG interface
J21 Input3.3Vanalog pins usable as GPIO's as alternative function

J31x analog inputs or GPIO, 1x dedicated analog input
1BJ4JTAG interface and 'JTAGEN' signal (5 I/O's)3.3VJTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks


Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

LIS3DH digital motion sensor, U4SPI interface, interrupt lines1x6 J43.3VGPIOs16bit SD-RAM memory interface
BankI/O's CountConnected toNotes13.3V6
241x14 pin header, JTAG interface
42 MByte serial configuration memory, U5FPGA configuration memory with active serial (AS) x1 interface
1J2-10, push button S1 low active reset input
2J1user GPIO's
8Pmod connector, J6user GPIO's
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6oscillator not fitted, footprints available for Microchip MEMS oscillator
591x14 pin header, J2GPIOs (2 I/O's (D11, D12) of bank 2 5 can be pulled-up to 3.3V (4K7 resistors) with 2 1 I/O 's (D12_R) of same Bank or pins can be shared)
33.3V8LEDs D2 ... D98 x red user LEDs
8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces
1push button S2user button
43.3V10pin headers J1, J3GPIOs
53.3V6pin headers J1GPIOs
63.3V8Pmod connector J6and 1 I/O (D11_R) of bank 6
6188 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3228 MByte SDRAM 166MHz, U216bit SDRAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A81x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J11 analog inputs or GPIO, 1 dedicated analog input
1B5pin header J44 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
88LEDs D2 ... D9Red user LEDs
6QSPI Flash memory, U56 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization
6FTDI FT2232H JTAG/UART Adapter, U36 pins configurable as GPIO/UART or other serial interfaces
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
73.3V198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
83.3V218 Mbyte SDRAM 166MHz, U21User button S2user configurable
1Reset button S1 and pin J2-10low active reset line for FPGA reconfiguration

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

JTAG SignalPin on Header J4Note

Table 4: optional JTAG pin header

JTAGEN2leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs

Table 4: optional JTAG pin header

On-board Peripherals

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N Winbond W74M64FVSSIQ with 16 64 MBit (2 8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 SPI interface.

chip selectAS_DCLK
Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 21, DATA1CSASF_DATA0CSFPGA bank 18, pin H2B3
Data outchip select
Pin 56, DATA0CLKASF_ASDOCLKFPGA bank 18, pin C1A3Data inclock
Pin 15, nCSSI/IO0ASF_NCSDIFPGA bank 18, pin D2A2data in / out

FPGA bank 18, pin H1


Table 5: Serial configuration memory interface connections




data in / out, configuration dual-purpose pin of FPGA
Pin 3, WP/IO2DEVCLRNFPGA bank 8, pin B9data in / out, configuration dual-purpose pin of FPGA
Pin 2, SO/IO1F_DOFPGA bank 8, pin B2data in / out

Table 5: Quad SPI Flash memory interface


The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2 . This in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 7 3 and 8 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 83-
Bank address inputs

BA0 / BA1

bank 83

Data input/output

DQ0 ... DQ15

bank 76

Data mask

DQM0 ... DQM1

bank 76

ClockCLKbank 73
Control Signals


bank 83

Chip select


bank 83

Clock enable


bank 83

Row Address Strobe


bank 83

Column Address Strobe

WEbank 83Write Enable

Table 6: 16bit SDRAM memory interface


The FTDI chip U3 converts signals from USB2 .0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 I/O's of channel A and 6 I/O's of Channel B are routed to FPGA bank 3 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.


FTDI Chip U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0TCKFPGA bank 11B, pin H3G2
JTAG interface
Pin 13, ADBUS1TDIFPGA bank 11B, pin H4F5
Pin 14, ADBUS2TDOFPGA bank 11B, pin J4F6
Pin 15, ADBUS3TMSPin 20, ADBUS7ADBUS7FPGA bank 3, pin N8user configurable

FPGA bank 1, pin J5

Pin 17, ADBUS4ADBUS4FPGA bank 3, pin M8user configurable

1B, pin G1

Pin 32, BDBUS0BDBUS0FPGA bank 38, pin A4user configurable
Pin 33, BDBUS1BDBUS1FPGA bank 38, pin B4
user configurable
Pin 34, BDBUS2BDBUS2FPGA bank 38, pin B5user configurable
Pin 35, BDBUS3BDBUS3FPGA bank 38, pin A6user configurable
Pin 37, BDBUS4BDBUS4FPGA bank 38, pin B6
user configurable
Pin 38, BDBUS5BDBUS5FPGA bank 38, pin A7user configurable

Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0003 TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Accelerometer U4 PinSignal Schematic NameConnected toNotes
Pin 11, INT1SEN_INT1FPGA bank 13, pin B1J5
Interrupt lines
Pin 9, INT2SEN_INT2FPGA bank 13, pin C2L4
Pin 6, SDA/SDI/SDOSEN_SDIFPGA bank 13, pin G2J7SPI interface


FPGA bank 13, pin G1K5

Pin 4, SCL/SPCSEN_SPCFPGA bank 13, pin F3J6
Pin 8, CSSEN_CSFPGA bank 13, pin D1L5
Pin 13, ADC3ADC35VSense 5V input voltage


Clock SourceSchematic NameFrequencyClock Input Destination
Microchip MEMS Oscillator, U7CLK12M12.0000 MHzFTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin M2H6
optional Microchip MEMS Oscillator, U6 (not fitted)CLK_X-FPGA SoC bank 62, pin E15G5

Table 9: Clock sources overview


LEDColorSignal Schematic NameFPGANotes
D1Green--Indicating 3.3V board supply voltage
D2Red'LED1'bank 68, pin M6pin A8user
D3Red'LED2'bank 68, pin T4pin A9user
D4Red'LED3'bank 68, pin T3A11user
D5Red'LED4'bank 68, pin R3A10user
D6Red'LED5'bank 68, pin T2pin B10user
D7Red'LED6'bank 68, pin R4C9user
D8Red'LED7'bank 68, pin N5pin C10user
D9Red'LED8'bank 68, pin N3pin D8user
D10Red'CONF_DONE'bank 68, pin H14C5indication configuration is DONE when LED is off


ButtonSignal Schematic NameFPGANotes
S1'USER_BTN'bank 38, pin N6E6user configurable
S2'RESET'bank 18, pin H5E7system FPGA reset

Table 11: Push buttons of the module


The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEI0003 TEI0001 module needs one single power supply of 5.0V nominal.


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titleFigure 3: Power Distribution Diagram
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Power Consumption


Table 12: Module power consumption Diagram
diagramNameTEI0003 Power distribution diagram

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Power Consumption

FPGADesignTypical Power, 25C ambient
Intel MAX 10 10M08 FPGA SoCNot configuredTBD*

Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.


Bank Voltages



Voltage Range

123.3Vall bank voltages fixed

Table 14: FPGA SoC VCCO bank voltages





Reference document

VIN supply voltage (5.0V nominal)




EP53A7HQI / EP53A7LQI datasheet
I/O Input voltage for FPGA I/O bank-0.54.212VIntel Cyclone MAX 10 LP datasheet

Storage Temperature




LED R6C-AL1M2VY/3T datasheet


ParameterMinMaxUnitsReference document
VIN supply voltage (5.0V nominal)4.755.25Vsame as USB-VBUS specification
I/O Input voltage for FPGA I/O bank–0.53.6VIntel Cyclone MAX 10 LP datasheet
Operating temperature range0+70


Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Please check Intel Cyclone MAX 10 LP datasheet  for complete list of absolute maximum and recommended operating ratings for the FPGA device.

Physical Dimensions


maximum and recommended operating ratings for the FPGA device.

Physical Dimensions

  • Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

  • PCB thickness: ca. 1.65mm

  • Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.


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titleFigure 4: Module physical dimensions drawing

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Revision History

Hardware Revision History



PCNDocumentation Link
-03Current available revision-TEI0001-03


First Production Release


Table 17: Module hardware revision history


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titleFigure 5: Module hardware revision number

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Document Change History




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Ali Naseri

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