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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.
Key Features
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Requirements
Software
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Hardware
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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*used as reference |
Note: Design contains also Board Part Files for TE0803 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
anchor | Table_HWC |
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title-alignment | center |
title | Hardware Carrier |
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*used as reference
Additional HW Requirements:
anchor | Table_AHW |
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title-alignment | center |
title | Additional Hardware |
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Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL P2421
Can be used to get access to console which is show on DP
USB was tested with USB memory stick
Ethernet works with DHCP, but can be setup also manually
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
anchor | Table_DS |
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title-alignment | center |
title | Design sources |
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<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
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Note: Design contains also Board Part Files for TE0803 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
Additional Sources
anchor | Table_ADS |
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title-alignment | center |
title | Additional design sources |
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Prebuilt
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File | File-Extension | Description | ||||||||||||
BIF-File | *.bif | File with description to generate Bin-File | ||||||||||||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | ||||||||||||
BIT-File | *.bit | FPGA (PL Part) Configuration File | ||||||||||||
Boot Script-File | *.scr | Distro Boot Script file | ||||||||||||
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | ||||||||||||
Debian SD-Image | *.img | Debian Image for SD-Card | ||||||||||||
Diverse Reports | --- | Report files in different formats | ||||||||||||
Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | ||||||||||||
LabTools Project-File | *.lpr | Vivado Labtools Project File | ||||||||||||
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | ||||||||||||
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | ||||||||||||
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | ||||||||||||
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems
Carrier Model | Notes |
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TEBF0808* | Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended |
*used as reference
Additional HW Requirements:
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For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Additional Sources
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Prebuilt
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Reference Design is available on:
Design Flow
scroll-pdf | true |
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scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide)
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
- Important: Use Board Part Files, which ends with *_tebf0808
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
- Press 0 and enter to start "Module Selection Guide" Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
- Important: Use Board Part Files, which ends with *_tebf0808
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications design and bootable files, which are defined in "test_board\sw_lib\apps_list.csvexport files into "<project folder>\prebuilt\hardware\<short name>") TE::swhw_runbuild_vitisdesign -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block | ||||||
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide) |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note |
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Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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TE::hw_build_design -export_prebuilt |
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
Launch
export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis (recommended)
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
- Copy PetaLinux build image files to prebuilt folder
Select create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Page properties hidden true id Comments
Note:
- Programming and Startup procedure
Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Get prebuilt boot binaries
This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze
- ...
- Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script
generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::
sw_
run_
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0808 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
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Note: See TRM of the Carrier, which is used. |
Tip |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
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1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
Linux
Open Serial Console (e.g. putty)select COM Port
Info |
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Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
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# password default disabled with 2021.2 petalinux release
petalinux login: root
Password: root |
Info |
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Note: Wait until Linux boot finished |
You can use Linux shell now.
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i2cdetect -y -r 0 (check I2C Bus, replace 0 with other bus number is also possible)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check)
lspci (PCIe check) |
vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0803
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0808 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (JTAG XMOD)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr- (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional with TEBF0808) Connect SATA Disc
- (Optional with TEBF0808) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional with TEBF0808) Connect Network Cable
Power On PCB
Expand title boot process 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password disabled petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to Zynq
Vivado Hardware Manager
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RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Set Enable to send Write date over RGPIO interface.
- Control:
- LEDs: XMOD 2 (without green dot) and HD LED are accessible.
- CAN_S
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System Design - Vivado
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Block Design
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PS Interfaces
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Activated interfaces:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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# system controller ip
#LED_HD SC0 J3:31
#LED_XMOD SC17 J3:48
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S SC16 J3:46 B26_L1_N
set_property PACKAGE_PIN G14 [get_ports BASE_sc0 |
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Vivado Hardware Manager
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RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Set Enable to send Write date over RGPIO interface.
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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# system controller ip #LED_HD SC0 J3:31 #LED_XMOD SC17 J3:48 #CAN RX SC19 J3:52 B26_L11_P #CAN TX SC18 J3:50 B26_L11_N #CAN S SC16 J3:46 B26_L1_N set_property PACKAGE_PIN G14 [get_ports BASE_sc0] set_property PACKAGE_PIN D15 [get_ports BASE_sc5] set_property PACKAGE_PIN H13 [get_ports BASE_sc6] set_property PACKAGE_PIN H14D15 [get_ports BASE_sc7sc5] set_property PACKAGE_PIN A13H13 [get_ports BASE_sc10_iosc6] set_property PACKAGE_PIN B13H14 [get_ports BASE_sc11sc7] set_property PACKAGE_PIN A14A13 [get_ports BASE_sc10_sc12io] set_property PACKAGE_PIN B13 [get_ports BASE_sc11] set_property PACKAGE_PIN A14 [get_ports BASE_sc12] set_property PACKAGE_PIN B14 [get_ports BASE_sc13] set_property PACKAGE_PIN F13 [get_ports BASE_sc14] set_property PACKAGE_PIN G13 [get_ports BASE_sc15] set_property PACKAGE_PIN A15 [get_ports BASE_sc16] set_property PACKAGE_PIN B15 [get_ports BASE_sc17] set_property PACKAGE_PIN J14 [get_ports BASE_sc18] set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # Audio Codec #LRCLK J3:49 #BCLK J3:51 #DAC_SDATA J3:53 #ADC_SDATA J3:55 set_property PACKAGE_PIN L13 [get_ports I2S_lrclk ] set_property PACKAGE_PIN L14 [get_ports I2S_bclk ] set_property PACKAGE_PIN E15 [get_ports I2S_sdin ] set_property PACKAGE_PIN F15 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ] |
Software Design - Vitis
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# MGTs only for ZU4/5 Devices
# Y6 MGT_224_CLK0_P -> B2B,J3-61 -> TEBF0808-04a_B230_CLK_P/CLK7_P -> B2B,J2-13 -> floating
# Y5 MGT_224_CLK0_N -> B2B,J3-59 -> TEBF0808-04a_B230_CLK_N/CLK7_N -> B2B,J2-15 -> floating
# V6 MGT_224_CLK1_P -> U5,38 -> Si5338 -> CLK1
# V5 MGT_224_CLK1_N -> U5,37 -> Si5338 -> CLK1
#set_property PACKAGE_PIN Y6 [get_ports {MGT_CLK_IN_clk_p[0]}]
#set_property PACKAGE_PIN V6 [get_ports {MGT_CLK_IN_clk_p[1]}] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloader------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2022TE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20212022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 20212022.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2021.2 FSBL General:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20212022.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashpmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: TE modified 2021.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 20212022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
hello_
fsbl_flashte0803
Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0803
Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- adjust Ethernet MAC Address (not necessary with the next version)
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3PART2_NAMESIZE="bootscr"0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_ENV_OVERWRITE=y
- CONFIG_SYS_I2C_EEPROM_ADDR=0x50
- CONFIG_SYS_I2C_EEPROM_BUS=7
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- # CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
Change platform-top.h:
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/include/ "system-conf.dtsi"
/ {
chosen {
xlnx,eeprom = &eeprom;
};
};
/*------------------ gtr --------------------*/
//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
/ {
refclk3:psgtr_dp_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <27000000>;
};
refclk2:psgtr_pcie_usb_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <100000000>;
};
//refclk1:psgtr_unused_clock {
// compatible = "fixed-clock";
// #clock-cells = <0x00>;
// clock-frequency = <100000000>;
//};
refclk0:psgtr_sata_clock {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <150000000>;
};
};
&psgtr {
clocks = <&refclk0 &refclk2 &refclk3>;
/* ref clk instances used per lane */
clock-names = "ref0\0ref2\0ref3";
};
/*------------------ SD --------------------*/
&sdhci0 {
// disable-wp;
no-1-8-v;
};
&sdhci1 {
// disable-wp;
no-1-8-v;
};
/*------------------ USB --------------------*/
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
phy-names = "usb2-phy","usb3-phy";
maximum-speed = "super-speed";
};
/*------------------ ETH PHY --------------------*/
&gem3 {
phy-handle = <&phy0>;
phy0: phy0@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
/*------------------ QSPI --------------------*/
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/*------------------ I2C --------------------*/
&i2c0 {
i2cswitch@73 { // u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x73>;
i2c-mux-idle-disconnect;
i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 { // SFP TEBF0808 PCF8574DWR
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c@2 { // PCIe
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { // SFP1 TEBF0808
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 {// SFP2 TEBF0808
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { // TEBF0808 EEPROM
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
eeprom: eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
i2c@6 { // TEBF0808 FMC
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
i2c@7 { // TEBF0808 USB HUB
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
i2cswitch@77 { // u
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x77>;
i2c-mux-idle-disconnect;
i2c@0 { // TEBF0808 PMOD P1
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
i2c@1 { // i2c Audio Codec
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
/*
adau1761: adau1761@38 {
compatible = "adi,adau1761";
reg = <0x38>;
};
*/
};
i2c@2 { // TEBF0808 Firefly A
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c@3 { // TEBF0808 Firefly B
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
i2c@4 { //Module PLL Si5338 or SI5345
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
i2c@5 { //TEBF0808 CPLD
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
i2c@6 { //TEBF0808 Firefly PCF8574DWR
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
i2c@7 { // TEBF0808 PMOD P3
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
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- NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0803_TEBF0808"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_ZYNQ_MAC_IN_EEPROM is not set
- CONFIG_NET_RANDOM_ETHADDR is not set
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
- Identification
- CONFIG_IDENT_STRING=" TE0803_TEBF0808"
Change platform-top.h:
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/include/ "system-conf.dtsi"
/*------------------ gtr --------------------*/
//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
/ {
refclk3:psgtr_dp_clock {
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/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; //refclk1:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000><27000000>; //}; refclk0refclk2:psgtr_pcie_satausb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000><100000000>; }; }; &psgtr //refclk1:psgtr_unused_clock { clocks = <&refclk0 &refclk2 &refclk3>// compatible = "fixed-clock"; //* ref clk instances used per lane */ clock#clock-namescells = "ref0\0ref2\0ref3"; }; /*------------------ SD --------------------*/ &sdhci0 { // disable-wp; <0x00>; // no-1-8-vclock-frequency = <100000000>; //}; &sdhci1 refclk0:psgtr_sata_clock { // disable-wp; compatible no-1-8-v= "fixed-clock"; }; /*------------------ USB --------------------*/ &dwc3_0 { status#clock-cells = "okay"<0x00>; dr_modeclock-frequency = "host" <150000000>; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed}; }; &psgtr { clocks = <&refclk0 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref0\0ref2\0ref3"; }; /*------------------ ETH PHYSD --------------------*/ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { sdhci0 { device_type =// "ethernetdisable-phy"wp; no-1-8-v; }; &sdhci1 { reg = <1>// disable-wp; }no-1-8-v; }; /*------------------- QSPIUSB --------------------*/ &qspidwc3_0 { #address-cellsstatus = <1>"okay"; #size-cellsdr_mode = <0>; status = "okay"host"; flash0: flash@0 {snps,usb3_lpm_capable; compatible = "jedec,spi-nor"snps,dis_u3_susphy_quirk; reg = <0x0>snps,dis_u2_susphy_quirk; #address-cellsphy-names = <1>"usb2-phy","usb3-phy"; #size-cellsmaximum-speed = <1>"super-speed"; }; }; /*------------------ ETH I2CPHY --------------------*/ &i2c0gem3 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnectdelete-property/ local-mac-address; phy-handle = <&phy0>; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassemblednvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; #address-cells = <1>; phy0: phy0@1 { device_type = #size-cells = <0>; "ethernet-phy"; reg = <0><1>; }; }; /*----------------- SATA }; i2c@1 { // SFP TEBF0808 PCF8574DWRPHY --------------------*/ &sata { #address-cellsceva,p0-burst-params = <1><0x13084a06>; #size-cellsceva,p0-cominit-params = <0><0x18401828>; regceva,p0-comwake-params = <1><0x614080e>; }; i2c@2 { // PCIe #address-cellsceva,p0-retry-params = <1><0x96a43ffc>; #size-cellsceva,p1-burst-params = <0><0x13084a06>; regceva,p1-cominit-params = <2><0x18401828>; }; i2c@3 { // SFP1 TEBF0808ceva,p1-comwake-params = <0x614080e>; #address-cellsceva,p1-retry-params = <1><0x96a43ffc>; }; /*-------------------- QSPI ---------------------*/ &qspi { #size#address-cells = <0><1>; #size-cells = <0>; status reg = <3>"okay"; flash0: flash@0 };{ i2c@4compatible {// SFP2 TEBF0808= "jedec,spi-nor"; reg #address-cells = <1><0x0>; #size#address-cells = <0><1>; reg #size-cells = <4><1>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 i2c@5 { // TEBF0808 EEPROMu compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <5><0x73>; i2c-mux-idle-disconnect; eeprom: eeprom@50 i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled compatiblereg = "atmel,24c08"<0>; }; reg = <0x50>;i2c@1 { // SFP TEBF0808 PCF8574DWR reg = }<1>; }; i2c@6i2c@2 { // TEBF0808 FMC PCIe #address-cellsreg = <1><2>; }; #size-cells = <0>; i2c@3 { // SFP1 TEBF0808 reg = <6><3>; }; i2c@7i2c@4 { // SFP2 TEBF0808 USB HUB #address-cellsreg = <1><4>; }; #size-cells = <0>;i2c@5 { // TEBF0808 EEPROM reg = <7><5>; }; eeprom: eeprom@50 };{ i2cswitch@77 { // u compatible = "nxpmicrochip,pca9548"; #address-cells = <1>24aa025", "atmel,24c02"; #size-cells = <0>; reg = <0x77><0x50>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0><1>; reg = <0>;eth0_addr: eth-mac-addr@FA { }; i2c@1 { //reg i2c= Audio<0xFA Codec0x06>; #address-cells = <1>}; #size-cells = <0>}; reg = <1>}; i2c@6 { // TEBF0808 /*FMC adau1761:reg adau1761@38= {<6>; }; compatible = "adi,adau1761"; i2c@7 { // TEBF0808 USB HUB reg = <0x38><7>; }; }; i2cswitch@77 { // u */ compatible }= "nxp,pca9548"; i2c@2reg { // TEBF0808 Firefly A= <0x77>; #address-cells = <1>i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 #size-cells = <0>;PMOD P1 reg = <2><0>; }; i2c@3i2c@1 { // TEBF0808i2c FireflyAudio BCodec #address-cellsreg = <1>; #size-cells = <0>;/* regadau1761: =adau1761@38 <3>;{ }; i2c@4compatible { //Module PLL Si5338 or SI5345 = "adi,adau1761"; #address-cellsreg = <1><0x38>; #size-cells = <0>}; reg = <4>;*/ }; i2c@5i2c@2 { // TEBF0808 CPLDFirefly A #address-cellsreg = <1><2>; }; #size-cells = <0>; i2c@3 { // TEBF0808 Firefly B reg = <5><3>; }; i2c@6i2c@4 { //TEBF0808 Firefly PCF8574DWRModule PLL Si5338 or SI5345 #address-cellsreg = <1><4>; }; #size-cells = <0>; i2c@5 { //TEBF0808 CPLD reg = <6><5>; }; i2c@7i2c@6 { // TEBF0808 PMODFirefly P3PCF8574DWR #address-cellsreg = <1><6>; }; #size-cells = <0>; i2c@7 { // TEBF0808 PMOD P3 reg = <7>; }; }; }; |
FSBL patch
Must be add manually, see template |
Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
- # CONFIG_CPU_IDLE is not set# CONFIG_CPU_FREQ is not set
- CONFIG_EDAC_CORTEX_ARM64=y
- Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_HWMON is not set#
- CONFIG_NVME_TCP is not setCONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
- CONFIG_NVM=y
- _POLICY=0
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_auto-loginCONFIG_NVM_PBLK=y
- CONFIG_NVMADD_PBLKEXTRA_DEBUG=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_busybox-httpd=y
- USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
Note |
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te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5338) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
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SI5338
File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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Legal Notices
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