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Name / opt. VHD NameDirectionPinDescription
C_TCK     in30JTAG B2B
C_TDI     in32JTAG B2B
C_TDO     out1JTAG B2B
C_TMS     in29JTAG B2B
EN1       in27Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback
ERR_OUT   in4PS_ERROR_OUT, see ug1085
ERR_STATUSin5PS_ERROR_STATUS, see ug1085 / currently_not_used
JTAGEN    in26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
MODE      in25Boot Mode for Zynq/ZynqMP Devices (Flash or SD)
MODE0     out12ZynqMP Boot Mode Pin 0
MODE1     out13ZynqMP Boot Mode Pin 1
MODE2     out14ZynqMP Boot Mode Pin 2
MODE3     out16ZynqMP Boot Mode Pin  3
NOSEQ     inout23/ currently_not_usedusage CPLD Variant depends
PGOOD     out28Module Power Good.
PHY_LED1  in17ETH PHY LED1
TCK     out9JTAG ZynqMP
TDI       out8JTAG ZynqMP
TDO       in10JTAG ZynqMP
TMS       out11JTAG ZynqMP
X0        out20FPGA IO / Firmware Variant
X1        out21FPGA IO / PHY_LED1

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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Boot Mode

2 Boot Modes can be selected via B2B Pin Mode. For other options Firmware update is necessary. Trenz Electronic provides currently 2 4 Firmware variants, one for SD and /JTAG, one for JTAG/QSPI, one for SD/QSPI and SD/QSPI/JTAG usage.

One
ModeJTAG/QSPI-VariantSD/JTAG-Variant
ZeroJTAGBoot from SD

SD/QSPI

(default Firmware)

SD/QSPI/JTAG
lowJTAGBoot from SDBoot from SDJTAG Mode, if NOSEQ* is high otherwise boot from SD
highBoot from FlashJTAGBoot from FlashJTAG Mode, if NOSEQ* is high otherwise boot from Flash

For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.

Note

Set Boot Mode to JTAG, A special FSBL is provided on 2017.4 or newer reference designs to write boot image to QSPI with Xilinx tools (Vivado or SDK) on Boot Mode unequal JTAG .


Note

NOSEQ*: Please check the carrierboard documentation, before using the SD/QSPI/JTAG  firmware variant on TE0820. In the most cases special carrier CPLD firmware is needed.

Power

PGOOD is EN1 and not ER_OUT. There is no additional power management controlled by CPLD.

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X0/X1 Pin

PHY_LED1
PinDescription
X0Firmware Variant: 0 SD boot, 1: QSPIX1*indicate firmware variant and NOSEQ status
X1PHY_LED1

*It's recommended to forward this signal to a carrier LED if status check is needed.

Firmware VariantBlink sequenceCondition
QSPI/JTAG*oooooooif boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0'
JTAG/SD**ooooooif boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0'
QSPI/SD****oooo/************oooo if NOSEQ='1' or ******** if NOSEQ='0'
SD/QSPI/JTAG***oooooif boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0'


Appx. A: Change History

Revision Changes

  • REV02 to REV03
    • new Boot Mode variants
    • new X0 status blink sequencing
  • REV01 to REV02
    • Boot Mode variants
    • X1
    • Remove ERR_STATUS

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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dateFormatyyyy-MM-dd

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current-version
prefixv.


REV02REV03REV02, REV01
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  • Revision 03 working in process
2018-01-10v.10REV02REV02, REV01John Hartfiel
  • update description - PHY LED correction
2017-08-21v.9REV02REV02, REV01John Hartfiel
  • Revision 02 finished
  • small text updates
2017-08-17v.8REV02REV02, REV01John Hartfiel
  • Revision 02 working in process
  • Boot Mode
  • X1 output
2017-06-08v.4REV01REV01John Hartfiel
  • document style update
2017-03-06v.2REV01REV01John Hartfiel
  • Revision 01 finished
2017-03-06

v.1

REV01REV01

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created-user

  • Initial release
 All  

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modified-users

 

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