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Overview

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The Trenz Electronic TEM0001 is a low cost small-sized FPGA module integrating a Microsemi SmartFusion2 FPGA SoC and 8 MByte Flash memory for configuration and operation.

Key Features

• Microsemi SmartFusion2 SoC FPGA

• 8 MByte SDRAM

• 8 MByte QSPI Flash memory

• 25 MHz system clock and 32.768 KHz auxiliary clock
• JTAG and UART over Micro USB2 connector
• 1x 3-pin header for Live Probes
• 1x PMOD header providing 8 GPIOs

• 2x 14-pin headers (2,54 mm pitch) providing 23 GPIOs

• 9 user LEDs

• 1 user push button
• 3.3V single power supply with on-board voltage regulators
• Size 61.5 x 25 mm
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEM0001-01 block diagram

Main Components

Figure 2: TEM0001-01 FPGA module

1. Microsemi SmartFusion2 FPGA SoC, U5
2. 8 Mbyte SDRAM 166MHz, U2
3. Micro USB2 B socket (receptacle), J9
4. Switch button (reset), S1
5. Switch button (user), S2
6. Red LED (user), D10
7. Green LED (indicating supply voltage), D1
8. 8x red LEDs (user), D2 - D9
9. FTDI USB2 to JTAG/UART adapter, U3
10. 8 Mbyte QSPI Flash memory, U1
11. 32.768 KHz auxiliary crystal oscillator, Y1
12. 25 MHz main crystal oscillator, Y2
13. 1x14 pin header (2.54mm pitch), J2
14. 1x6 pin header (2.54mm pitch), J4
15. 3-pin header (2.54mm pitch), J3
16. 1x14 pin header (2.54mm pitch), J1
17. 2x6 Pmod connector, J6

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins of the FPGA are set to QSPI mode, hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks  connected to the board's pin headers and connectors:

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Table 2: General overview of PL I/O signals connected to pin headers and connectors

Single ended I/O banks

Table 3: General overview of single ended I/O banks

JTAG Interface

JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

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Table 4: JTAG interface signals

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:

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Table 5: QSPI interface signals

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Winbond Serial NOR Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SDRAM

The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM IC U2. This SDRAM IC is connected to the FPGA bank 4 and 7 via 16bit memory interface with 166MHz clock frequency and CL3 CAS latency.

FTDI FT2232H IC

The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.

FTDI FT2232H IC is used in MPPSE Mode for JTAG, 6 I/O's of Channel B are routed to the bank 1 of the FPGA SoC and are usable as for example UART and other standard serial or parallel interfaces. The configuration of FTDI FT2232H IC can be stored to and loaded from to the configuration EEPROM U9, which is not programmed on delivery state.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

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Table 6: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

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Table 7: LEDs of the module

Push Buttons

The TEM0001 FPGA module is equipped with two push buttons S1 and S2:

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Table 8: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

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Figure 3: Power Distribution Diagram

Power Consumption

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Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Technical Specifications

Absolute Maximum Ratings

Table 10: Absolute maximum ratings

Recommended Operating Conditions

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Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

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Figure 4: Module physical dimensions drawing

Revision History

Hardware Revision History

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Figure 5: Module hardware revision number

Document Change History

Table 13: Document change history

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