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Table 2: General overview of PL single ended I/O signals connected to pin headers and connectors
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FPGA I/O banks
| Bank | VCCIO | I/O's Count | Available on Connectors | Notes |
|---|---|---|---|---|
| 1 | 3.3V | 14 | 5 | 6 I/O's connected to FTDI chip, 1 I/O used for user button S2, 2 I/O's connected to red user LEDs D2 and D10. |
| 2 | 3.3V | 37 | 26 | 6 I/O's user for QSPI Flash, 5 I/O's connected to red user LEDs D3 ... D7. |
| 3 | 3.3V | 5 | 5 | Bank 3 is dedicated to JTAG interface. |
| 4 | 3.3V | 24 | 0 | 2 I/O's are dedicated to live probes, all other I/O's are used as memory interface. |
| 7 | 3.3V | 22 | 2 | 2 I/O's available on header J2, 2 I/O's connected to red user LEDs D8 and D9, all other I/O's are used as memory interface. |
Table 3: General overview of single ended FPGA I/O banks
JTAG Interface
JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.
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The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H ICchip.
FTDI FT2232H IC chip is used in MPPSE Mode mode for JTAG, 6 I/O's of Channel B are routed to the bank 1 of the FPGA SoC and are usable as for example UART and other standard serial or parallel interfaces. The configuration of FTDI FT2232H IC can be stored to and loaded from to the configuration EEPROM U9, which is not programmed on delivery state.
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| Button | Signal Schematic Name | FPGA | Notes |
|---|---|---|---|
| S1 | 'USER_BTN' | B19Indicating | 3.3V module supply voltageuser configurable |
| S2 | 'RESET' | E18System | Resetsystem reset |
Table 8: Push buttons of the module
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Overview
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