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Table 1: Initial delivery state of programmable devices on the module

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By default the configuration mode pins of the FPGA are set to QSPI mode, hence the FPGA is configured from serial NOR flash Flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

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On-module QSPI flash memory (U7) is provided by Winbond Serial NOR Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SDRAM

The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM IC chip U2. This SDRAM IC chip is connected to the FPGA bank 4 and 7 via 16bit 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to the bank 1 of the FPGA SoC and are usable configured as for example UART and other standard serial or parallel interfacesUART interface. The configuration of FTDI FT2232H IC can be stored to and loaded from to the configuration EEPROM U9, which is not programmed on delivery statechip is pre-programmed on the EEPROM U9.

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

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