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Table 3: General overview of FPGA I/O banks
JTAG Interface
Primary JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.
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| JTAG Signal | Pin on Header J4 | Note |
|---|---|---|
| TCK | 3 | - |
| TDI | 5 | - |
| TDO | 4 | - |
| TMS | 6 | - |
| JTAGSEL | 2 | The JTAGSEL pin of SmartFusion2 device depends on the used JTAG programmer. |
Table 4: optional second JTAG interface signalsor GPIO (JTAGSEL dependent)
QSPI Interface
The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:
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Overview
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