Page History
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Revision History
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Date | Vivado | Project Built | Authors | Description | ||||||
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2018- | 1101- | 1418 | 2017.24 | TE0807-test_board_noprebuilt-vivado_2017. | 24-build_05_ | 2017111411552420180118152119.zip TE0807-test_board-vivado_2017. | 24-build_05_ | 2017111411551120180118152104.zip | John Hartfiel | initial release |
Release Notes and Know Issues
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2017-11-14 | 2017.2 | TE0807-test_board_noprebuilt-vivado_2017.2-build_05_20171114115524.zip TE0807-test_board-vivado_2017.2-build_05_20171114115511.zip | John Hartfiel |
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Release Notes and Know Issues
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Software | Version | Note |
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Vivado | 2017.24 | needed |
SDK | 2017.24 | needed |
Hardware
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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TE0807-01-ES2 | es2 | REV01 | 2GB | 64MB |
Note: Design contains also Board Part Files for TE0803TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.
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Reference Design is available on:
Design Flow
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- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not contains ends with *_tebf0808
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
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- Select JTAG as Boot Mode (see Carrier Description and ZynqMP TRM)
- Connect JTAG to Host PC
- Power OnConnect JTAG and power on carrier with module
- Open Vivado Hardware Manager with Auto Connect
- Right Click to FPGA Device XCU... and select Add Configuration Memory Device
- Select correct Flash Typ (see schematics or FPGAFLASHTYP on test_board/board_files/TE0808_board_files.csv)
- Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setupOpen Program Configuration Memory Device - Configuration file: test_board/prebuilt/boot_image/<short dir>/hello_te0803/Boot.bin
- Zynq FSBL: test_board/prebuilt/software/<short dir>/zynqmp_fsbl.elf Program Device Flash
Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with SDK Debugger into device, see:
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Type | Note |
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DDR | |
QSPI | MIO |
UART0 | MIO, please select other one, if you have connected uart to second controller or other MIO |
SWDT0..1 | |
TTC0..3 |
Constrains
Basic module constrains
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For SDK project creation, follow instructions from:
Application
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zynqmp_fsbl
Xilinx default FSBL
zynqmp_fsbl_flash
TE modified 2017.4 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
Hello
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TE0807
Hello TE0803 TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
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2017-11-14 | v.3 | John Hartfiel | Release 2017.2 | ||||||||||||||||||||||
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