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Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

DateVersionChangesAuthor
2023-02-072.2
  • added column 'Firmware release' in 'Document Change History' table
  • changed template revision from list to table
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware

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Overview

Firmware for PCB CPLD with designator U7. CPLD Device in Chain: LCMX02-256HC

Feature Summary

  • Power Monitoring
  • Reset
  • LED
  • JTAG routing

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
C_

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LED 

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out17

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none3.3VGreen LED D4, blinking pattern according to different states
DONEin28up3.3VFPGA Done signal, also connected to green LED D3. Is OFF when FPGA configured.
F_TCK / C_TCKout9none3.3VFPGA JTAG
F_TDI / C_TDIout21none3.3VFPGA JTAG
F_TDO / C_TDOin5none3.3VFPGA JTAG
F_TMS / C_TMSout4none3.3VFPGA JTAG
GND
10
3.3VGND
GND
11
3.3VGND
GND
12
3.3VGND
GND
13
3.3VGND
GND
14
3.3Vconnected to GND
JTAGMODE
26
3.3VEnable JTAG access to CPLD for Firmware update (

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LOW-'0' : JTAG signales routed to module,

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HIGH-'1' : CPLD access)
MODEin16
3.3V/ currently_not_used
PG_ALLin27up3.3VPower sense from 1V/1.8V/3.3V/3.3VIN
PGOODinout25

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up3.3VPower Good. Low, if power failed, internal pullup activated

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PROG_Bout23none3.3VFPGA Prog_B
RESINin8up3.3Vexternal reset from B2B
TCK / M_TCKin30none3.3VB2B JTAG
TDI / M_TDIin32up3.3VB2B JTAG
TDO / M_TDOout1none3.3VB2B JTAG
TMS / M_TMSin29up3.3VB2B JTAG
XIO

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in20none3.3VFPGA IO from Bank14 H26

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, Can be used to control LED D4 if no error state occurs

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Reset

PROG_B is triggered by RESIN

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or PG_ALL.

Power

PG_ALL is used

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to trigger PROG_B

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Reset in case of power failure. This case is also indicated by the green LED D4.

PGOOD is set low, if PG_ALL failed otherwise high impedance. Internal pullup is activated.

PGOOD can be drive to low from carrier, this will be indicated by LED subsequency only.

LED

LED D4 Green
StatusBlink SequencePriority

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Comment

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Reset******** ~3Hz1

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external Reset is set

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Power failed*****ooo2

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PG_ALL Problem (1.8V

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or 3.3V)
PGOOD Low****oooo3PGOOD is set low from carrier or the power monitor U11 noticed a power failure
DONE*ooooooo4Module not programmed
idleOFF5Module ready and programmed. In this case LED D4 can be controlled by FPGA - XIO Signal

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Generate new entry:
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Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV2 to REV03

  • added JTAG DELAY and Pullmode constraints
  • XIO can be used to control LED D4

CPLD REV01 to REV02

  • add PGOOD functionality
  • new LED status sequence

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescriptionFirmware release
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date
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infoTypeCurrent

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version
prefixv.
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Flat

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REV03 REV02

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- REV05

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  • Update Document Style

2023-12-13

v.7

REV03 REV02 - REV05

Waldemar Hanemann

  • Revision 03
2023-12-13
SC-PGM-(TE0741-005_SC0741-003_20231213.zip)

2018-08-29

v.4 REV02 REV02,REV03

John Hartfiel

  • Revision 02 released
2018-08-29 (SC-PGM-TE0741-0203_SC0741-02_20180829.zip)

2028-03-08

v.2REV01 REV02,REV03John Hartfiel
  • Revision 01 
2014-07-02

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v.1

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Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

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