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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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- removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
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- extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
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- added boot process for Microblaze
- minor typos, formatting
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- carrier reference note
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- added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
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- Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
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Important General Note:
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- Design Flow
- formatting
- Launch
- formatting
- minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.src description
- added USB for programming
- swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
- Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
- add fix table of content
- add table size as macro
- removed page initial creator
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Export PDF to download, if vivado revision is
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Overview
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Microblaze Design with linux example.
Refer to http://trenz.org/te0710-info for the current online version of this manual and other available documentation.
For directly getting started with the prebuilt files jump to the section Launch.
Key Features
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- initial release
Release Notes and Know Issues
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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title-alignment | center |
title | Hardware Modules |
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Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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Content
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For general structure and usage of the reference design, see Project Delivery -
Design Sources
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Additional Sources
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Prebuilt
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*.srec
Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of
AMD Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on
AMD Design Flow.
See also:
- Xilinx Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by
AMD Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and
AMD install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
- Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0xA00000 (increase automatically generate Boot partition), increase image size to A:, see Config
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf and image.ub from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on
AMD Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze
- ...
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- (Optional) BlockRam Firmware Update
Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf"
Code Block language bash theme Midnight TE::hw_build_design -export_prebuilt TE::sw_run_vitis -all
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
AMD documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)
- Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot
- Reboot (if not done automatically)
SD-Boot mode
Not used on this Example.
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
Expand title boot process 1. FPGA Loads Bitfile from Flash,
2. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while)
Image Added
3. U-boot loads Linux from QSPI Flash into DDR
Page properties hidden true id Comments This step depends on
AMD Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Linux
- Open Serial Console (e.g. putty)
- Speed: 9600
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight
root@petalinux:
Info Note: Wait until Linux boot finished, autologin is activated.
You can use Linux shell now.
Code Block language bash theme Midnight udhcpc (ETH0 check)
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- User LED Control
- ETH Power Down
- Monitoring:
- ETH Link Status
- MicroBlaze Reset Status
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Block Design
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Constraints
Basic module constraints
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
Design specific constraints
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## set_property PACKAGE_PIN G3 [get_ports {LED_RED_XA_SC[0]}] ## set_property IOSTANDARD LVCMOS15 [get_ports {LED_RED_XA_SC[0]}] set_property PACKAGE_PIN T10 [get_ports {ETH2_LINK_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_LINK_LED[0]}] set_property PACKAGE_PIN V15 [get_ports {ETH1_LINK_LED[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_LINK_LED[0]}] set_property PACKAGE_PIN T18 [get_ports {ETH1_PD_N[0]}] set_property PACKAGE_PIN D10 [get_ports {ETH2_PD_N[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_PD_N[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_PD_N[0]}] set_property PACKAGE_PIN L15 [get_ports {LED_RED_D3[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_RED_D3[0]}] #EEPROM onewire (MAC ADDRESS) |
set_property |
IOSTANDARD |
LVCMOS33 [get_ports |
EEPROM_ |
tri_ |
io] set_property PACKAGE_PIN |
D9 [get_ports |
EEPROM_ |
tri_ |
io] ## IIC Interface set_property PACKAGE_PIN |
G3 [get_ports |
IIC_0_ |
sda_ |
io] set_property |
PACKAGE_PIN |
J5 [get_ports |
IIC_0_ |
scl_ |
io] set_property IOSTANDARD |
LVCMOS15 [get_ports |
IIC_0_ |
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LVCMOS15 [get_ports |
IIC_0_ |
sda_ |
io] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2021.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2021.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2021.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2021.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a |
Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
spi_bootloader
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM.
Descriptions:
- Modified Files: bootloader.c
- Changes:
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
hello_te0710
Hello TE0710 is a
Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf
is generated with PetaLinux. Vivado is used to generate *.mcs
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE =
0xD00000 (kernel)
(Set kernel flash Address to 0xA00000 (fpga+boot+bootenv) and Kernel size to
0xD00000)
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
- # CONFIG_PHY_ATHEROS is not set
- # CONFIG_PHY_BROADCOM is not set
- # CONFIG_PHY_DAVICOM is not set
- # CONFIG_PHY_LXT is not set
- # CONFIG_PHY_MICREL_KSZ90X1 is not set
- # CONFIG_PHY_MICREL is not set
- # CONFIG_PHY_NATSEMI is not set
- # CONFIG_PHY_REALTEK is not set
- CONFIG_RGMII=y
Busybox
Start with petalinux-config -c busybox
- Miscellaneous Utilities → activate i2cget, i2cset, i2cdetect
Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:
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#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000 |
Device Tree
Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:
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/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &axi_quad_spi_0 { #address-cells = <1>; #size-cells = <0>; flash0: flash@0 { compatible = "jedec,spi-nor"; spi-tx-bus-width=<1>; spi-rx-bus-width=<4>; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <25000000>; }; }; /* ETH PHY */ &axi_ethernetlite_0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <1>; }; }; }; /* ETH PHY 2nd |
*/ &axi_ethernetlite_1 { phy-handle = <&phy1>; mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { device_type = "ethernet-phy"; reg = <1>; }; }; }; /* i2c */ &axi_iic_0 { clock-frequency = <100000>; |
status = "okay";
};
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Kernel
Start with petalinux-config -c kernel
Changes:
- No changes.
Rootfs
Start with petalinux-config -c rootfs
Changes:
- # CONFIG_dropbear is not set
- # CONFIG_dropbear-dev is not set
- # CONFIG_dropbear-dbg is not set
- # CONFIG_packagegroup-core-ssh-dropbear is not set
- # CONFIG_packagegroup-core-ssh-dropbear-dev is not set
- # CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
- # CONFIG_imagefeature-ssh
- -server-dropbear is not set
CONFIG_imagefeature-serial-autologin-root = y
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
eeprom
eeprom is a simple bash script implemented in petalinux as an application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address
sdtoscript(Beta)
sdtoscript is a petalinux C-Application that reads raw data at a predetermined address from a <2GB sd card and writes it to a file in petalinux. It is only suitable for low level raw data transfer.
Additional Software
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No additional software is needed.
App. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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