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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
Date | Version | Changes | Author |
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20222023- | 0112- | 2514 | 3.1. | 10- removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-1417 | - updated according to Vivado 2023.2
| ma | 2023-06-13 | 3.1.16 | - Design flow:
- added alternative programming files in Petalinux
- added chapter FSBL Patch in Software Design - Petalinux
| ma | 2023-06-01 | 3.1. | 9- extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 15 | - removed u-boot.dtb from Design flow
| ma | 2023-06-01 | 2021-06-28 | 3.1. | 8- added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-0114 | - expandable lists for revision history and supported hardware
| wh | 2023-05-25 | 3.1. | 7 | jh | 2021-05-0413 | - updated according to Vivado 2022.2
| ma | 2023-02-08 | 3.1. | 612 | | zynq_ from zynq_fsbl- content of
- Special FSBL for QSPI programming
| ma | 20212022- | 0408- | 2824 | 3.1. | 5- added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-2711 | - Modification from link "available short link"
| ma | 2022-01-25 | 3.1.10 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1. | 4- Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma | 3.1.3 | | ma | 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.src description
- added USB for programming
| ma | 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma | 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
|
|
9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | - Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma |
| 3.1.3 | | ma |
| 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.scr description
- added USB for programming
| ma |
| 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
|
|
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
|
|
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Important General Note: |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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Microblaze Design with linux example.
Refer to http://trenz.org/te0710-info for the current online version of this manual and other available documentation.
For directly getting started with the prebuilt files jump to the section Launch.
Key Features
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Notes : - Add basic key features, which can be tested with the design
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Excerpt |
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- Vitis/Vivado 20212023.2
- PetaLinux
- MicroBlaze
- SPI ELF Bootloader
- Flash
- MIG
- ETH(ETH1 and ETH2)
- LED
- EEPROM MACSDcard interface(Beta, not for boot!)
- I2C Interface to CPLD
- JTAG to AXI Master
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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title | Design Revision History |
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cellHighlighting | true |
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Date | Vivado | Project Built | Authors | Description |
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2024-02-19 | 2023.2 | TE0710-test_board_noprebuilt-vivado_2023.2-build_4_20240219100859.zip TE0710-test_board-vivado_2023.2-build_4_20240219100859.zip | Waldemar Hanemann | | 2022-02-16 | 2021.2 | TE0710-test_board_noprebuilt-vivado_2021.2-build_11_20220216112910.zip TE0710-test_board-vivado_2021.2-build_11_20220216112910.zip | Waldemar Hanemann | - new spi bootloader
by Henrik Brix Andersen - adjusted offsets
| 2022-02-04 | 2021.2 | TE0710-test_board-vivado_2021.2-build_11_20220208153036.zip TE0710-test_board_noprebuilt-vivado_2021.2-build_11_20220208153036.zip
| Waldemar Hanemann | - 2021.2 update
- document style update
- added boot script
- added eeprom interface for MAC address read-out
- added simple sd card interface
- added 2nd Ethernet Interface
| 2020-04-21 | 2019.2 | TE0710-test_board-vivado_2019.2-build_10_20200421063949.zip TE0710-test_board_noprebuilt-vivado_2019.2-build_10_20200421064005.zip | John Hartfiel | | 2018-03-29 | 2017.4 | te0710-test_board-vivado_2017.4-build_07_20180329130739.zip te0710-test_board_noprebuilt-vivado_2017.4- |
| build_07_20180329130757.zip | John Hartfiel | |
Release Notes and Know Issuesbuild_07_20180329130757.zip | John Hartfiel | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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title | Known Issues |
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sortEnabled | false |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Requirements
Software
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Notes : - list of software which was used to generate the design
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title | Software |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Software | Version | Note |
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Vitis | 2023.2 | needed, Vivado is included into Vitis installation | PetaLinux | 2023.2 | needed |
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Hardware
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Notes :add known Design issues and general notes for the current revisiondo not delete known issue, add fixed version time stamp if issue fixed: - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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| KIHWM | title-alignment | center |
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title |
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| Known Issues | Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
Requirements
Software
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Notes : - list of software which was used to generate the design
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anchor | Table_SW |
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title-alignment | center |
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title | Software |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Software | Version | Note |
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Vitis | 2021.2 | needed, Vivado is included into Vitis installation |
PetaLinux | 2021.2 | needed |
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0710-02-35-2CF | 35_2cf_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-35-2IF | 35_2if_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-100-2CF | 100_2cf_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-100-2IF | 100_2if_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-72I21-A | 100_2if_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-S001 | 100_2cf_512mb | REV02 | 512MB | 32MB | NA | NA | no ETH-PHY | TE0710-02-42I21-A | 35_2if_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-S003 | 35_2if_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-03-42C21-A | 35_2cf_512mb | REV03 |
|
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Hardware
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Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Scroll Title |
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anchor | Table_HWM |
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title-alignment | center |
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title | Hardware Modules |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0710-02-35-2CF | 35_2cf_512mb | REV02 less IOs TE071002352IF 512mb REV02 less IOs TE0710021002CF 512mb REV02 NA TE0710021002IF*512mb REV02 NA
Design supports following carriers:
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anchor | Table_HWC |
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title-alignment | center |
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title | Hardware Carrier |
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orientation | portrait |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Carrier Model | Notes |
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TE0701 |
| TE0703* | used as reference carrier | TE0705 |
| TE0706 |
| TEBA0841 |
|
*used as reference |
Additional HW Requirements:
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anchor | Table_AHW |
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title-alignment | center |
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title | Additional Hardware |
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orientation | portrait |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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repeatTableHeaders | default |
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
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Additional Sources
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anchor | Table_ADS |
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title-alignment | center |
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title | Additional design sources |
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orientation | portrait |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files |
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| Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software | -Application-File*.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-Application-File | *. | srecelf | Converted Software Application for Zynq or MicroBlaze Processor Systems |
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Scroll Title |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebuilt content) |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx AMD Software for the same Project.
Reference Design is available on:
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx AMD Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx AMD Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block |
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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|
TE::hw_build_design -export_prebuilt |
Info |
---|
Using Vivado GUI is the same, except file export to prebuilt folder. |
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
- Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0xA00000 (increase automatically generate Boot partition), increase image size to A:, see Config
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
Generate Programming Files with Vitis
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") |
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|
TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note |
---|
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
- (Optional) BlockRam Firmware Update
Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf"
Code Block |
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language | bash |
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theme | Midnight |
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TE::hw_build_design -export_prebuilt
TE::sw_run_vitis -all |
Launch
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Note: - Programming and Startup procedure
|
Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx AMD documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info |
---|
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)
- Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script programs BOOT.bin on QSPI flash) |
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|
TE::pr_program_flash -swapp u-boot |
- Reboot (if not done automatically)
SD-Boot mode
Not used on this Example.
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
---|
Note: See TRM of the Carrier, which is used. |
Tip |
---|
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr |
Power On PCB
Expand |
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1. FPGA Loads Bitfile from Flash, 2. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while) Image RemovedImage Added
3. U-boot loads Linux from QSPI Flash into DDR |
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This step depends on Xilinx AMD Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
... |
Linux
- Open Serial Console (e.g. putty)
- Speed: 9600
select COM Port
Info |
---|
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
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language | bash |
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theme | Midnight |
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petalinux login: root
Password: rootroot@petalinux: |
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Note: Wait until Linux boot finished, autologin is activated.
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You can use Linux shell now.
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language | bash |
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theme | Midnight |
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udhcpc (ETH0 check)
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Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- User LED Control
- ETH Power Down
- Monitoring:
- ETH Link Status
- MicroBlaze Reset Status
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anchor | Figure_VHM |
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title-alignment | center |
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title | Vivado_Hardware_Manager |
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System Design - Vivado Scroll Ignore |
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scroll-pdf | true |
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Block Design
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anchor | Figure_BD |
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title-alignment | center |
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title | Block DesignDesign |
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draw.io Diagram |
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border | true |
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diagramName | TE0710_Blockdesign2023.2 |
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simpleViewer | false |
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width | 600 |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 3144 |
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revision | 1 |
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Constraints
Basic module constraints
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language | ruby |
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title | _i_bitgen_common.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
Design specific constraints
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language | ruby |
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title | _i_io.xdc |
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## set_property PACKAGE_PIN G3 [get_ports {LED_RED_XA_SC[0]}]
## set_property IOSTANDARD LVCMOS15 [get_ports {LED_RED_XA_SC[0]}]
set_property PACKAGE_PIN T10 [get_ports {ETH2_LINK_LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_LINK_LED[0]}]
set_property PACKAGE_PIN V15 [get_ports {ETH1_LINK_LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_LINK_LED[0]}]
set_property PACKAGE_PIN T18 [get_ports {ETH1_PD_N[0]}]
set_property PACKAGE_PIN D10 [get_ports {ETH2_PD_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_PD_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_PD_N[0]}]
set_property PACKAGE_PIN L15 [get_ports {LED_RED_D3[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_RED_D3[0]}]
#EEPROM onewire (MAC ADDRESS)
set_property IOSTANDARD LVCMOS33 [get_ports EEPROM_tri_io]
set_property PACKAGE_PIN D9 [get_ports EEPROM_tri_io]
#SD Card SPI
set_property PACKAGE_PIN B9 [get_ports sclk_o_0]
set_property IOSTANDARD LVCMOS33 [get_ports sclk_o_0]
set_property PACKAGE_PINIOSTANDARD C11LVCMOS33 [get_ports csEEPROM_botri_0io]
set_property PACKAGE_PIN A9D9 [get_ports misoEEPROM_itri_0io]
## IIC Interface
set_property PACKAGE_PIN C9G3 [get_ports mosiIIC_0_osda_0io]
set_property IOSTANDARDPACKAGE_PIN LVCMOS33J5 [get_ports mosiIIC_0_oscl_0io]
set_property IOSTANDARD LVCMOS33LVCMOS15 [get_ports misoIIC_0_iscl_0io]
set_property IOSTANDARD LVCMOS33LVCMOS15 [get_ports csIIC_0_bosda_0io]
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Software Design - Vitis
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For Vitis project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2021.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: fsblTE modified 2021.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
fsbl_flashTE modified 2021.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2021.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
spi_bootloader
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.
Descriptions:
- Modified Files: bootloader.c
- Changes:
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
hello_te0710
Hello TE0710 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate u-boot.srec(obsolete). Vivado is generated with PetaLinux. Vivado is used to generate *.mcs
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000 0xD00000 (kernel)
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
- # CONFIG_PHY_ATHEROS is not set
- # CONFIG_PHY_BROADCOM is not set
- # CONFIG_PHY_DAVICOM is not set
- # CONFIG_PHY_LXT is not set
- # CONFIG_PHY_MICREL_KSZ90X1 is not set
- # CONFIG_PHY_MICREL is not set
- # CONFIG_PHY_NATSEMI is not set
- # CONFIG_PHY_REALTEK is not set
- CONFIG_RGMII=y
Busybox
Start with petalinux-config -c busybox
- Miscellaneous Utilities → activate i2cget, i2cset, i2cdetect
Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:
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#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000 |
Device Tree
Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:
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/include/ "system-conf.dtsi"
/ {
};
/* QSPI PHY */
&axi_quad_spi_0 {
#address-cells = <1>;
#size-cells = <0>;
flash0: flash@0 {
compatible = "jedec,spi-nor";
spi-tx-bus-width=<1>;
spi-rx-bus-width=<4>;
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <25000000>;
};
};
/* ETH PHY */
&axi_ethernetlite_0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
/* ETH PHY 2nd PHY */
&axi_ethernetlite_1 {
phy-handle = <&phy1>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy1: phy@1 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
/* i2c */
&axi_iic_0 {
clock-frequency = <100000>;
status = "okay";
};
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Kernel
Start with petalinux-config -c kernel
Changes:
Rootfs
Start with petalinux-config -c rootfs
Changes:
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
eeprom
eeprom is a simple bash script implemented in petalinux as an application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address.
sdtoscript(Beta)
sdtoscript is a petalinux C-Application that reads raw data at a predetermined address from a <2GB sd card and writes it to a file in petalinux. It is only suitable for low level raw data transfer.
Additional Software
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scroll-pdf | true |
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Page properties |
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
App. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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anchor | Table_dch |
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title | Document change history. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | 2*,*,3*,4* |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Document Revision | Authors | Description |
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| infoType | | Modified |
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type | Flat |
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| infoType | Current | current-version |
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| current-version |
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prefix | v. |
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| type | Flat |
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Page info |
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infoType | Modified by |
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type | Flat Page info |
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| modified-user |
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| modified-user |
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| | | | | | 2022-02-16 | v.8 | Waldemar Hanemann | - new spi bootloader
by Henrik Brix Andersen - adjusted offsets
| 2022-02-14 | v.7 | Waldemar Hanemann
| - 2021.2 update
- document style update
- added boot script
- added eeprom interface for MAC address read-out
- added simple sd card interface
- added 2nd Ethernet Interface
| 2020-04-21 | v.5 | | - Release 2019.2
- Docu update
| 2019-03-29 | v.4 | John Hartfiel | | 2019-03-29 | v.1 | | | --- | All | Page info |
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| modified-users |
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| modified-users |
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| --- |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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