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VITA 57.1 FMC HPC standard compatible
Four SFP+ 10Gb (850nm) ports
Low jitter programmable clock generator
Intel(Altera) Max10 FPGA 10M08SAU169C8G
Status LED (green)

Block Diagram

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Figure 1: TEF0008-01 block diagram.

Main Components

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Figure 2: TEF0008-01 FMC overview.

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On-board I²C devices are connected to the HPC FMC Pin C30 SCL and pin C31 SDA which are reserved for I²C. Level shift and for PLL and SFP+ I²C is done by the FPGA as well as MUX for SFP+. Addresses for on-board devices are listed in the table below:

I²C Device	I2C Address	Notes
J4, SFP+
J5, SFP+
J6, SFP+
J7, SFP+
U2, Si5345A	1101001	Level shifted via MAX10 FPGA
U4, EEPROM	10100xx	Last digits determined by carrier board via HPC FMC (C34 GA0, C35 GA1).

Table 7: I²C slave device addresses.

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There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338ASi5345A, U2) to generate various reference clocks for the module.

Not connected.

Si5338A Pin

Si5345A Pin

Signal Name / Description	Connected To	Direction	Note
IN0	Reference input clock.-	U1	Input	25.000000 MHz oscillator, Si8208AI
IN1	-	Not connected.	Input	Not used.
IN2	-

GND

IN4

Not connected.	Input	Not used.
IN3

Reference input clock.

U3, pin 3Input25.000000 MHz oscillator, Si8208AI.

		Input
A1

-

GND

Input

I²C slave device address LSB

.

IN5

-

Not connected.InputNot used

.

IN6


	-	GND	Input	Not used.

CLK0A

OUT0

CLK1_P

U1, R23

Output

FPGA bank 45.

CLK0B

OUT1

CLK1_N

-

U1, P23

Output

FPGA bank 45.

CLK1AMGT_CLK1_N


OUT2		U1, V5	Output	FPGA MGT bank 225 reference clock.

CLK1BMGT_CLK1_P

OUT3

-

U1, V6

Output

FPGA MGT bank 225 reference clock.

CLK2AMGT_CLK3_N

OUT4

-

U1, AB5

Output

FPGA MGT bank 224 reference clock.

CLK2BMGT_CLK3_P

OUT5

-

U1, AB6

Output

FPGA MGT bank 224 reference clock.

CLK3A

CLK0_P

U1, pin T24

OUT6

-

Output

FPGA bank 45.

CLK3B

OUT7

CLK0_N

GBTCLK0	U1, pin T25	Output	FPGA bank 45.
OUT8	CLK0
OUT9	CLK1

Table 8: Programmable quad PLL clock generator inputs and outputs.

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Trenz Electronic Documentation

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Block Diagram

Main Components