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Table of Contents

Overview


The Trenz Electronic TEF0008 is a FPGA to Mezzanine Card (FMC) based on VITA 57.1 FMC HPC Standard, with four SFP+ 10Gb ports for fiber optical SFP modules. It is inteded for use on a FMC HPC carrier and can not be used stand-alone.


Key Features

  • Four SFP+ 10Gb ports
  • HPC FMC connector
  • Low jitter programmable clock generator
  • Intel(Altera) Max10 FPGA 10M08SAU169C8G
  • Status LED (green)

Block Diagram


Figure 1: TEF0008 block diagram.

Main Components


Figure 2: TEF0008 FMC overview.


Table 1: TEF0008 main components.

  1. MAX10 FPGA, U5
  2. Programmable low jitter clock generator Si5354A, U2
  3. Status LED (green), D1
  4. 3.3V to 1.8V DCDC converter, U6
  5. Quad SFP+ cage and connectors, J4-J7
  6. 1x6 pin header for JTAG programming of FPGA (3.3V), J3
  7. 1x3 pin header for I²C (1.8V), J1
  8. XTAL 54.0000 MHz (CX3225SB), Y1
  9. Oszillator 25.000000 MHz (SiT8008B), U1
  10. HPC FMC connector, J2
  11. 128KBit EEPROM, U4
  12. Testpoints Max10, TP7-TP9
  13. Testpoints JTAG, TP1-TP4
  14. Testpoints Power, TP5, TP6, TP10

Initial Delivery State

Storage device name

Content

Notes

Max10 FPGA 10M08SAU169C8G

ProgrammedU5. Level shifter and controlller functions.

Clock generator

Si5345A-B-GM

Programmed

U2. OUT0 25MHz, OUT2 125MHz, OUT7 156.25 MHz, OUT8 156.25MHz, OUT9 125MHz.

EEPROM

24LC128-I/ST

emptyU4, IPMI and VITA57.1 compatible.

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The MAX10 FPGA boots form its internal configuration flash memory, which is programmable via JTAG (J3).

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the FPGA I/O bank and B2B connector: 

BankTypeB2B ConnectorI/O Signal CountBank VoltageNotes
3GPI/OsJ220 I/OsVADJSupplied by the carrier board.

Table 2: General overview of I/O signals connected to the B2B connectors.


MGT Lanes

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TD/RD) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, and HPC FMC Pin:

LaneSFP+Signal NameHPC FMC Pin
0J4
  • SFPA_RD_P
  • SFPA_RD_N
  • SFPA_TD_P
  • SFPA_TD_N
  • J2-C6
  • J2-C7
  • J2-C2
  • J2-C3
1J5
  • SFPB_RD_P
  • SFPB_RD_N
  • SFPB_TD_P
  • SFPB_TD_N
  • J2-A2
  • J2-A3
  • J2-A22
  • J2-A23
2J6
  • SFPC_RD_P
  • SFPC_RD_N
  • SFPC_TD_P
  • SFPC_TD_N
  • J2-A6
  • J2-A7
  • J2-A26
  • J2-A27
3J7
  • SFPD_RD_P
  • SFPD_RD_N
  • SFPD_TD_P
  • SFPD_TD_N
  • J2-A10
  • J2-A11
  • J2-A30
  • J2-A31

Table 3: MGT lanes.

Below are listed MGT banks reference clock sources.

Clock signalSourceHPC FMC PinNotes
GBTCLK0_PU2-51J2-D4, GBTCLK0_M2C_POn-board Si5345A.
GBTCLK0_NU2-50J2-D5, GBTCLK0_M2C_NOn-board Si5345A.
GBTCLK1_PU2-31J2-B20, GBTCLK1_M2C_POn-board Si5345A.
GBTCLK1_NU2-30J2-B21, GBTCLK1_M2C_NOn-board Si5345A.

Table 4: MGT reference clock sources.

SFP+ Control Interface

Following table contains a brief description of the control and status signals of the SFP+ connectors:

Signal Schematic NameFPGA DirectionDescriptionLogic
SFPx_TX_DISABLEOutputSFP Enabled / DisabledLow active
SFPx_LOSInputLoss of receiver signalHigh active
SFPx_RS0OutputFull RX bandwidthLow active
SFPx_RS1OutputReduced RX bandwidthLow active
SFPx_M-DEF0InputModule present / not presentLow active
SFPx_TX_FAULTInputFault / Normal OperationHigh active
SFPx_SDABiDir2-wire Serial Interface Data-
SFPx_SCLOutput (BiDir)2-wire Serial Interface Clock-

Table 5: Overview of SFP control Signals.


Up to 100kHz the modules operate without clock streching. Therfore SCL can be implemented as driven by Master only.

JTAG Interface

JTAG access to the MAX10 FPGA is provided through HPC FMC Connector and an additional pin header connector as well as testpoints.

JTAG Signal

HPC FMC Pin

Pin HeaderTestpoints
TCKJ2-D29J3-4TP2
TDIJ2-D33J3-2TP1
TDOJ2-D30J3-3TP3
TMSJ2-D31J3-1TP4

Table 6: JTAG interface signals.


I2C Interface

Despite the EEPROM U4 all other on-board I2C devices are connected to the MAX10 FPGA for level shift and I²C MUX. Addresses for devices are listed in the table below. The EEPROM is accessed via the FMC connector.

I2C DeviceI2C AddressNotes
 J4, SFP+ 1100001 / 1100000 Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation.
 J5, SFP+ 1100001 / 1100000 Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation.
 J6, SFP+ 1100001 / 1100000 Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation.
 J7, SFP+ 1100001 / 1100000 Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation.
U2, Si5345A1101001Level shifted via MAX10 FPGA, Device select via MAX10 FPGA implementation.
U4, EEPROM10100xxLast digits determined by carrier board via HPC FMC (C34 GA0, C35 GA1).

Table 7: I2C slave device addresses.

HPC FMC Connector

The following table lists all on the FMC connector assigned net names.



ABCDEFGHJK
1GNDNetJ2_B1GNDPG_C2MGNDPG_M2CGND
GND
2SFPB_RD_PGNDSFPA_TD_PGND
GNDCLK1_PGND
GND
3SFPB_RD_NGNDSFPA_TD_NGND
GNDCLK1_NGND
GND
4GND
GNDGBTCLK0_PGND
GNDCLK0_PGNDCLK2_P
5GND
GNDGBTCLK0_NGND
GNDCLK0_NGNDCLK2_N
6SFPC_RD_PGNDSFPA_RD_PGND
GNDLA00_PGND
GND
7SFPC_RD_NGNDSFPA_RD_NGND

LA00_NLA02_P

8GND
GNDLA01_PGND
GNDLA02_NGND
9GND
GNDLA01_N
GNDLA03_PGND
GND
10SFPD_RD_PGNDLA06_PGND

LA03_NLA04_P

11SFPD_RD_NGNDLA06_NLA05_PGND
GNDLA04_NGND
12GND
GNDLA05_N
GNDLA08_PGND
GND
13GND
GNDGND

LA08_NLA07_P

14
GND
LA09_PGND
GNDLA07_NGND
15
GND
LA09_N
GND
GND
GND
16GND
GNDGND





17GND
GND
GND
GND
GND
18
GND


GND
GND
GND
19
GND
GND





20GNDGBTCLK1_PGND
GND
GND
GND
21GNDGBTCLK1_NGND

GND
GND
GND
22SFPB_TD_PGND
GND





23SFPB_TD_NGND

GND
GND
GND
24GND
GND

GND
GND
GND
25GND
GNDGND





26SFPC_TD_PGND

GND
GND
GND
27SFPC_TD_NGND


GND
GND
GND
28GND
GNDGND





29GND
GNDTCKGND
GND
GND
30SFPD_TD_PGNDFMC_SCLTDI
GND
GND
GND
31SFPD_TD_NGNDFMC_SDATDO





32GND
GND3P3VAUXGND
GND
GND
33GND
GNDTMS
GND
GND
GND
34
GNDGA0






35
GND12VGA1GND
GND
GND
36GND
GND3P3V
GND
GND
GND
37GND
12VGND





38
GNDGND3P3VGND
GND
GND
39
GND3P3VGNDVADJGNDVADJGND
GND
40GND
GND3P3VGNDVADJGNDVADJGND

Table 8: HPC FMC Connector pin assignment.


On-board Peripherals


MAX10 FPGA

The MAX10 FPGA (10M08SAU169C8G) is used as SFP control, level shifter and I2C MUX. For a detailed description see TEF0008 MAX10.

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator on-board (Si5345A, U2) to generate reference clocks for the module. Programming can be done using I2C via PIN header J1. The I2C bus is also routed to the MAX10 FPGA.

Si5345A Pin
Signal Name / Description
Connected ToDirectionNoteDefault

IN0

Reference input clock.

U1Input25.000000 MHz oscillator, Si8208AI
IN1-Not connected.InputNot used.

IN2

-

Not connected.InputNot used.

IN3

CLK2J2-K4/K5InputHPC FMC configured as C2M clock.

A1

-

GNDInputI2C slave device address LSB.
XAXB-Y1Input54.0000 MHz XTAL CX3225SB

OUT0

CLKPLL2F

U5-H6/G5Output

FPGA bank 2.

25MHz
OUT1-Not connected.OutputNot used.---
OUT2GBTCLK1J2-B20/B21OutputM2C via HPC FMC.125MHz
OUT3-Not connected.OutputNot used.---
OUT4-Not connected.OutputNot used.---
OUT5-Not connected.OutputNot used.---
OUT6

-

Not connected.

Output

Not used.---
OUT7GBTCLK0J2-D4/D5OutputM2C via HPC FMC.156.25MHz
OUT8CLK0J2-H4/H5OutputM2C via HPC FMC.156.25MHz
OUT9CLK1J2-G2/G3OutputM2C via HPC FMC.125MHz

 Table 9: Programmable clock generator inputs and outputs.

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008AI oscillator, U1-25.000000 MHzU2-63/64
Carrier board via HPC FMC J2-K4/K5CLK2Defined by carrier.U2-61/62

Table 10: Reference clock signals.

EEPROM

A Microchip 24LC128-I/LC serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector (SCL C30, SDA C31).

On-board LED

LED ColorConnected toDescription and Notes
D1Green U5-C2 (bank 1A)Depending on FPGA design. With the shipped FPGA design it is on, if at least one SFP is connected.

Table 11: On-board LED.

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module depends on the design running on the FPGA.



3P3VTBD*
VADJ (at 1.8V)TBD*

3P3VAUX

TBD*

Table 12: Typical power consumption.

 * TBD - To Be Determined with reference design setup.

Power Distribution Dependencies


Figure 3: Module power distribution diagram.

Power Rails

Power Rail Name

HPC FMC Connector (J2)

Direction

Notes
3P3VD36, D38, D40, C39InputSupply voltage from carrier board.
1.8V-OutputModule on-board 1.8V voltage supply (Max 1A).

3P3VAUX

D32InputSupply voltage from carrier board.

VADJ

H40, G39, F40, E39InputSupply voltage from carrier board.
12VC35, C37InputNot used supply voltage from carrier board.

Table 13: Module power rails.

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

1A3P3V

3.3V

-
1B3P3V3.3V-
21.8V1.8V-
3VADJCarrier supplied1.2V - 3.3V
53P3V3.3V-
63P3V3.3V-
83P3V3.3V-

Table 14: Module PL I/O bank voltages.


Variants Currently In Production

 Module VariantFPGA

Operating Temperature

Temperature Range
 TE0008-0210M08SAU169C8G0°C to +85°CExtended

Table 15: Module variants.

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

Storage temperature

-40

85

°C

-

Table 16: Module absolute maximum ratings.

Operating Temperature Ranges

Extended grade: 0°C to +85°C.

Physical Dimensions

  • Module size: 69 mm × 84 mm, SFP+ conector excluded (+ 5.5 mm). See Vita 57.1 standard.

  • PCB thickness: 1.6 mm.

  • Highest part on PCB top is 9.5 mm (SFP+ cage, excluded front plate),  bottom 1.4 mm (MAX10 FPGA). Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure 4: Module physical dimensions drawing

Mounting holes near the front pannel are not implemented due to physical restrictions caused by the SFP cage. The dimensions exceed in some area the by Vita 57.1 standard defined dimensions. In the middle region of the card the cage is higher than the specified max high for this area. Check carefully if the carrier card uses this space for other components conflicting mechanical.  The bottom side is at the high limit.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
2018-06-0602First production release

-

01

Prototypes



Table 17: Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 5: Module hardware revision number.

Document Change History


Date

Revision

Contributors

Description

  • add default CLK values also to SI section
  • changes on document change history style
2018-08-24v.38Martin Rohrmüller
  • Updated Table 15 and 17 to Rev02.

  • Added FMC connector pin assignment (Table 8).

2018-06-15


v.32


Martin Rohrmüller

  • Initial document.
---

all

  • ---

Table 18: Document change history.

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