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The Trenz Electronic TEF0008 is an FMC HPC (FPGA to Mezzanine Card / VITA 57.1) expansion card which offers four SFP+ 10 Gb ports for SFP modules which is intended for FMC HPC carrier usage and can not be used as stand-alone solution. An Altera MAX10 FPGA is onboard for control, management and custom purposes.
Refer to https://trenz.org/tef0008-info for current online available documentation.
Storage device name | Designator | Content | Notes |
|---|---|---|---|
Altera MAX10 FPGA | U5 | Firmware | For further information see TEF0008 MAX10 Firmware / TEF0008 MAX10. |
FMC FRU EEPROM | U4 | Not programmed | |
Clock generator | U2 | Programmed |
The programmable Clock Generator (Si5345A, U2) is programmed according to the table below.
It can be controlled via the PLL I2C bus (Pin header J1) or via the FPGA (MAX10 U5) as I2C controller.
Clock generator | OUT/IN put / Net Name / Destination/Source Device.Pin | IO Standard | Default Frequency in MHz | Notes |
|---|---|---|---|---|
Input | XA/XB / XAXB_P/XAXB_N / Y1.3/Y1.1 | Analog | 54 MHz | |
IN0 / IN0_P/IN0_N / U1.3/U1.2 | LVDS | 25 MHz | ||
IN1 / Not used | - | - | ||
IN2 / Not used | - | - | ||
IN3 / CLK2_C_P/CLK_2_N CLK2_P/CLK2_N / J2.K4/J2.K5 | LVDS | - | Frequency defined by carrier. | |
Output | OUT0 / CLKPLL2F_P/CLKPLL2F_N / U5.H6/U5.G5 | LVDS 1.8 V | 25 MHz | |
OUT1 / GCLKF_P/GCLKF_N / U5.H4/U5.H5 | LVDS 1.8 V | 125 MHz | ||
OUT2 / GBTCLK1_P/GBTCLK1_N / J2.B20/J2.B21 | LVDS 1.8 V | 125 MHz | ||
OUT3 / Not used | - | - | ||
OUT4 / Not used | - | - | ||
OUT5 / Not used | - | - | ||
OUT6 / Not used | - | - | ||
OUT7 / GBTCLK0_P/GBTCLK0_N / J2.D4/J2.D5 | LVDS 1.8 V | 156¼ MHz | ||
OUT8 / CLK0_P/CLK0_N / J2.H4/J2.H5 | LVDS 1.8 V | 156¼ MHz | ||
OUT9 / CLK1_P/CLK1_N / J2.G2/J2.G3 | LVDS 1.8 V | 125 MHz |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
FMC HPC | J2 | GPIO | 20x SE | |
FMC HPC | J2 | MGT | 4x GTX (RX/TX) | |
FMC HPC | J2 | JTAG | 4x SE | |
FMC HPC | J2 | I2C | 2x SE | |
SFP+ | J4 / J5 / J6 / J7 | MGT | 1x GTX (RX/TX) |
Test Point | REV03 | REV02 Signal | Notes | ||
|---|---|---|---|---|---|
Top | Bottom | Signal | |||
TP1 | x | TDI | |||
TP2 | x | TCK | |||
TP3 | x | TDO | |||
TP4 | x | TMS | |||
TP5 | x | GND | |||
TP6 | x | 3P3V | |||
TP7 | x | M10_RST | |||
TP8 | x | M10_TX | |||
TP9 | x | M10_RX | |||
TP10 | x | 1.8V | |||
TP11 | x | VADJ | Not used | ||
TP12 | x | 3P3VAUX | Not used | ||
Chip / Interface | Designator | Connected to | Notes |
|---|---|---|---|
FPGA | U5 |
| For further information see TEF0008 MAX10 Firmware / TEF0008 MAX10. |
Clock generator | U2 |
| |
FMC FRU EEPROM | U4 |
| |
Oscillator | U1 |
| 25 MHz |
Crystal | Y1 |
| 54 MHz |
Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.
Signal Name | Connector.Pin | Direction 1) | Description |
|---|---|---|---|
| I2C ( LA00_P / LA00_N / LA01_P ) | J2B.G6 / J2B.G7 / J2B.D8 | IN / IN / OUT | 3 wire I2C bus. SCL in / SDA in / SDA out. |
LA01_N / LA02_P /LA02_N | J2B.D9 / J2B.H7 / J2B.H8 | IN | Mux signals to select a SFP I2C canal. |
LA03_N / LA04_P | J2B.G10 / J2B.H10 | IN | SFP RS0 / RS1 signals. |
LA03_P | J2B.G9 | IN | SFP TX disable signals. |
LA04_N | J2B.H11 | OUT | SFP TX fault/error signal. |
LA05_N / LA06_N / LA07_N / LA08_N | J2B.D12 / J2B.C11 / J2B.H14 / J2B.G13 | OUT | SFP LOS A / LOS B / LOS C / LOS D signals. |
LA05_P / LA06_P / LA07_P / LA08_P | J2B.D11 / J2B.C10 / J2B.H13 / J2B.G12 | OUT | SFP A/B/C/D Inserted Flag |
PG_C2M | J2F.D1 | IN | Power good carrier to module. |
PG_M2C | J2F.F1 | OUT | Power good module to carrier. |
JTAG ( TMS / TDI / TDO / TCK ) | J3.1 / J3.2 / J3.3 / J3.4 | Signal dependent | JTAG for FPGA MAX10 U5. |
I2C ( PLL_SCL / PLL_SDA ) | J1.1 / J1.3 | Signal dependent | I2C for Programmable Clock Generator U2 and FPGA MAX10 U5. |
GA0 / GA1 | J2F.C34 / J2F.D35 | IN | Geographic addresses of FMC FRU EEPROM. |
I2C ( FMC_SCL / FMC_SDA ) | J2F.C30 / J2F.C31 | Signal dependent | I2C for FMC FRU EEPROM. |
- / LED D1 | U5.C2 | OUT | Signals that at least one SFP is connected. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
DIP switch group | DIP switch | Signal name | Description |
|---|---|---|---|
S1 | S1A | JTAG_EN | Enable/Disable JTAG interface to FPGA U5. |
S1B | USR_SW | User definable |
Power Rail Name / Schematic Name | Description | Connector.Pin | Direction 1) | Notes |
|---|---|---|---|---|
12V | Rail not used on module. | J2G.C35 / J2G.C37 | - | |
3P3V | Main module supply | J2G.D36 / J2G.D38 / J2G.D40 / J2G.C39 J3.6 | IN | max. 3 A |
VADJ | Adjustable voltage supply rail for FPGA GPIO bank 3. | J2G.H40 / J2G.G39 / J2G.F40 / J2G.E39 | IN | max. 4 A |
3P3VAUX | Auxiliary supply rail. | J2G.D32 | IN | max. 20 mA |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
0 | - | - | - | Configuration SoM signal setup. | |
1 | 3P3V | 3.3 V ±5 % | - | Apply main module supply. | |
VADJ | 3.3 V ±5 % | - | Apply adjustable voltage supply. | ||
3P3VAUX | 3.3 V ±5 % | - | Apply auxiliary supply. |
Warning!
The listed values ONLY reflect this board. Connected Carriers / SoMs / Boards are not considered.
Power Rail Name / Schematic Name | Description | Min | Max | Unit | Notes |
|---|---|---|---|---|---|
3P3V | Main module supply | -0.5 | 3.9 | V | |
VADJ | Adjustable voltage supply rail for FPGA GPIO bank 3. | -0.5 | 3.9 | V | |
3P3VAUX | Auxiliary supply rail | -0.5 | 6.5 | V |
*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).
Power Rail Name/ Schematic Name | Description | Min | Max | Units | Notes |
|---|---|---|---|---|---|
3P3V | Main module supply | 3.135 | 3.465 | V | |
VADJ | Adjustable voltage supply rail for FPGA GPIO bank 3. | 0 | 3.465 | V | |
3P3VAUX | Auxiliary supply rail | 3.135 | 3.465 | V |
Module size: 69.0 mm x 90.36 mm. Please download the assembly diagram for exact numbers.
| Trenz shop TEF0008 overview page | |
|---|---|
| English page | German page |
The hardware revision number can be found on the PCB together with the module's model number, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
2025-07 | 03 |
| |
2018-07 | 02 |
| |
2018-05 | 01 | Initial revision | - |
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
2026-07-016 | v.44 | Kilian Jahn |
|
2026-04-14 | v.43 | Martin Rohrmüller |
|
2025-10-29 | v.42 | Maksim Tserabei |
|
| 2025-10-29 | v.41 | Maksim Tserabei | updated according new REV03 |
| 2018-08-24 | v.38 | Martin Rohrmüller |
|
2018-06-15 | Martin Rohrmüller |
| |
| --- | all |
|
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