Table of contents
TEF0008 design for MAX10 FPGA U2: 10M08SAU169C8G.
- SFP Control
- I2C MUX
- level shifter
- LED Control
Firmware Revision and supported PCB Revision
See Document Change History.
|Name / opt. VHD Name||Direction||Pin||Description|
|A_LOS_i||In||H9||SFP A Signal Loss (HIGH indicates signal loss)|
|In||G9||SFP A Modul Absent (HIGH when module physically absent)|
|A_RS0_o||Out||J9||SFP A Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|A_RS1_o||Out||H8||SFP A Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|A_SCL_o||Out||K10||SFP A I2C Clock|
|A_SDA_io||Bidir||K11||SFP A I2C Data|
|Out||H10||SFP A (HIGH disables transmitter)|
|A_TX_FAULT_i||In||L12||SFP A Laser Fault (HIGH indicates fault)|
|B_LOS_i||In||K12||SFP B Signal Loss (HIGH indicates signal loss)|
|B_MDEF0_i||In||J13||SFP B Modul Absent (HIGH when module physically absent)|
|B_RS0_o||Out||J12||SFP B Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|B_RS1_o||Out||L13||SFP B Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|B_SCL_o||Out||H13||SFP B I2C Clock|
|SFP B I2C Data|
|B_TX_DIS_o||Out||G13||SFP B (HIGH disables transmitter)|
|In||G12||SFP B Laser Fault (HIGH indicates fault)|
|SFP C Signal Loss (HIGH indicates signal loss)|
|C_MDEF0_i||In||E12||SFP C Modul Absent (HIGH when module physically absent)|
|C_RS0_o||Out||F13||SFP C Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|C_RS1_o||Out||F9||SFP C Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|C_SCL_o||Out||E13||SFP C I2C Clock|
|C_SDA_io||Bidir||D11||SFP C I2C Data|
|C_TX_DIS_o||Out||D12||SFP C (HIGH disables transmitter)|
|C_TX_FAULT_i||In||C12||SFP C Laser Fault (HIGH indicates fault)|
|D_LOS_i||In||B11||SFP D Signal Loss (HIGH indicates signal loss)|
|In||B12||SFP D Modul Absent (HIGH when module physically absent)|
|D_RS0_o||Out||B13||SFP D Rate Select RX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|D_RS1_o||Out||C13||SFP D Rate Select TX (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)|
|D_SCL_o||Out||A12||SFP D I2C Clock|
|D_SDA_io||Bidir||F10||SFP D I2C Data|
|D_TX_DIS_o||Out||E9||SFP D (HIGH disables transmitter)|
|In||D9||SFP D Laser Fault (HIGH indicates fault)|
|LA01_N||In||J5||I2C GPIO MUX 0|
|In||M13||I2C GPIO MUX 1|
|In||M12||I2C GPIO MUX 2|
|LA04_N||Out||K7||TX Fault A+B+C+D|
|LA05_P||Out||K5||DEF0 A, SFP A Inserted Flag|
|LA06_P||Out||K6||DEF0 B, SFP B Inserted Flag|
|LA07_P||Out||N8||DEF0 C, SFP C Inserted Flag|
|LA08_P||Out||N7||DEF0 D, SFP D Inserted Flag|
- Input Signal LA03_N sets all four SFP RX modes (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)1
- Input Signal LA04_P sets all four SFP TX modes (LOW for 1000BASE-SX, HIGH for 10GBASE-SR)1
- Output Signals LA05_N, LA06_N, LA07_N and LA08_N indicate signal loss of SFP A, B, C and D respectively (HIGH indicates signal loss).
- Output Signals LA05_P, LA06_P, LA07_P and LA08_P indicate SFP A, B, C and D module absend (HIGH when module physically absent).
- Output Signal LA04_N is HIGH when at least one of the four SFPs indicate Laser fault.
- Input LA03_P HIGH sets for all SFPs where the module is physically available (MDEF0_i is LOW) the TX_DIS signal to LOW.2
1SFP Control and I2C register writes of RX/TX modes are couppled with a logical or. If at least one of them indicates HIGH the 10GBASE-SR is activated.
2Inverted control as we can not enable weak pulldown in MAX10, we use weak pullup. TX are all ENABLED at default power up, so the card is working with no FMC LA pin driven.
- LA00_P, LA00_N and LA01_P form a "three wire I2C" bus with seperate data in and output.
- LA01_N, LA02_P and LA02_N are used as selector for the MUX.
|100||Si5345 Clock Generator|
For I2C adresses see TEF0008 TRM.
LED is used as Status LED and is on if at least on SFP is connected.
MAX10 JTAG for programming is always enabled and accessible via the FMC connector, pin header J3 and testpoints.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
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