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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TD/RD) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, and HPC FMC Pin:
| Lane | SFP+ | Signal Name | HPC FMC Pin |
|---|---|---|---|
| 0 | J4 |
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| 1 | J5 |
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| 2 | J6 |
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| 3 | J7 |
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Table 4: MGT lanes.
Below are listed MGT banks reference clock sources.
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