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Follwowing table contains a brief description of the control and status signals of the SFP+ connectors:
Signal Schematic Name | FPGA Direction | Description | Logic |
---|---|---|---|
SFPx_TX_DISABLE | Output | SFP Enabled / Disabled | Low active |
SFPx_LOS | Input | Loss of receiver signal | High active |
SFPx_RS0 | Output | Full RX bandwidth | Low active |
SFPx_RS1 | Output | Reduced RX bandwidth | Low active |
SFPx_M-DEF0 | Input | Module present / not present | Low active |
SFPx_TX_FAULT | Input | Fault / Normal Operation | High active |
SFPx_SDA | BiDir | 2-wire Serial Interface Data | - |
SFPx_SCL | Output | 2-wire Serial Interface Clock | - |
Note |
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SCL signal is Master driven only, therefore clockstreching is not allowed. |
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I2C Device | I2C Address | Notes |
---|---|---|
J4, SFP+ | 1100010 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, SFP SFP Device select via MAX10 FPGA implementation. |
J5, SFP+ | 1100010 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, SFP SFP Device select via MAX10 FPGA implementation. |
J6, SFP+ | 1100010 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, SFP SFP Device select via MAX10 FPGA implementation. |
J7, SFP+ | 1100010 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, SFP Device select via MAX10 FPGA implementation. |
U2, Si5345A | 1101001 | Level shifted via MAX10 FPGA |
U4, EEPROM | 10100xx | Last digits determined by carrier board via HPC FMC (C34 GA0, C35 GA1). |
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