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Signal Schematic Name	FPGA Direction	Description	Logic
SFPx_TX_DISABLE	Output	SFP Enabled / Disabled	Low active
SFPx_LOS	Input	Loss of receiver signal	High active
SFPx_RS0	Output	Full RX bandwidth	Low active
SFPx_RS1	Output	Reduced RX bandwidth	Low active
SFPx_M-DEF0	Input	Module present / not present	Low active
SFPx_TX_FAULT	Input	Fault / Normal Operation	High active
SFPx_SDA	BiDir	2-wire Serial Interface Data	-
SFPx_SCL	Output (BiDir)	2-wire Serial Interface Clock	-

Note
Up to 100kHz the modules operate without clock streching. Therfore SCL can be implemented as driven by Master only.

JTAG access to the MAX10 FPGA is provided through HPC FMC Connector and an additional pin header connector as well as testpoints.

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