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Overview

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Refer to https://wiki.trenz-electronic.de/display/PD/TEB0911+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq UltrascaleUltraScale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM SO-DIMM socket with 64-bit wide data bus, 24 22 MGT Lanes lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard TEB0911 board exposes the pins of the Zynq MPSoC 's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq UltrascaleUltraScale+ MPSoC and for developing purposes. The motherboard board is capable to be fitted to a dedicated enclosure. On , whereby on the enclosure's rear and front panel, I/O's, LVDS-pairs and MGT interfaces lanes are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for , namely USB3.0, SFP+, SSD, GbE, etc.

Key Features

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Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.

Key Features

• Zynq UltraScale+ MPSoC
  • ZU6,ZU9 or ZU15 on 1156 Pin Package
• 64bit DDR4 SODIMM (PS connected)
• M2 PCIe SSD (1-Lane)
• eMMC (bootable)
• Dual QSPI Flash (bootable)
• System Controller(LCMXO2-7000HC)
  • Power Sequencing
  • IO Expander
• Configurable PLLs
• GTH/GTP Reference CLKs

Front Panel

• 4 x FMC
  • 4 GTH per FMC
  • 68 ZynqMP PL IO per FMC
• DisplayPort (2-Lanes)
• RJ34 ETH + Dual USB3 Combo
• Dual Stack SFP+
• SD (bootable)
• Status LEDs

Back Panel

• 2 x FMC
  • 4/2 GTH
  • 12 ZynqMP PL IO per FMC
  • 56 SC IO per FMC
• USB JTAG/UART ZynqMP
• USB JTAG/GPIO FMC
• CAN FD (DB9 Connector)
• SMA (external CLK)
• 5polig 24V power connector
• Single 24V main power supply
• 2x USB3 A Connector (Superspeed Host Port (Highspeed in USB2 mode))
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• Dual SFP+ Connector (2x1 Cage)
• DDR4-SDRAM SODIMM socket (64bit bus width)
• SSD (Solid State Disk) Connector
• CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
• 1x DisplayPort
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• All carrier board peripherals' I²C interfaces muxed to MPSoC's I²C interface
• 6x FMC HPC Connectors
• 6x FMC Fans
• 3x Optional 4-wire PWM fan connectors
• 10 output programmable PLL clock generator Si5345A
• Quad programmable PLL clock generator SI5338A
• 1x SMA coaxial connectors for reference clock signal input
• MicroSD-Socket (bootable)
• 32 Gbit (4 GByte) on-board eMMC flash (8 banks a 4 Gbit)
• System Controller CPLD Lattice MachXO2 7000 HC
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLD
• On-board DC-DC PowerSoCs and LDOs

Additional assembly options are available for cost or performance optimization upon request.

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Main Components

1. SFP+ 2x1 cage with integrated LED light pipes, J9
2. DisplayPort connector, J12
3. USB3 A 2x , RJ45 1x (stacked), J13
4. FMC connector (FMC B), J4
5. FMC B cooling fan, M2
6. FMC connector (FMC C), J8
7. FMC C cooling fan, M3
8. FMC connector (FMC D), J7
9. FMC D cooling fan, M4
10. FMC connector (FMC E), J6
11. FMC E cooling fan, M5
12. I²C programming header of on-board PLL clock generator U17, J22
13. 4-Wire PWM fan connector, J23
14. Main Power Jack 24V, J1
15. CAN bus D-SUB 9-pin male connector, J3
16. CAN bus 6-pin header male, J15
17. XMOD JTAG header for access to System Controller CPLD, J35
    
18. XMOD JTAG header for access to Zynq MPSoC, J24
19. 4-Wire PWM fan connector, J33
20. Battery Holder CR1220, B1
21. SMT SMA coaxial connector (PLL Si5345A U17 clock input), J25
22. Push Button, S1
23. Push Button, S2
24. DDR4 SO-DIMM socket, U3
25. 4-bit DIP-switch, S4
26. 4-bit DIP-switch, S3
27. FMC connector (FMC A), J10
28. FMC A cooling fan, M1
29. FMC connector (FMC F), J21
30. FMC F cooling fan, M6
31. NGFF M.2 PCIe socket (Key M), U2
32. SD Card socket, J11
33. User LEDs (3x green, 1x red) with LED light pipe, D13 ... D16
    
34. Green LEDs dedicated to USB3 hub U4, D17 ... D19
35. Red LED indicating FPGAs 'DONE' signal, D6
36. 4-Wire PWM fan connector, J2
37. Xilinx Zynq Ultrascale+ MPSoC, U1
    

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

Table 2: Available boot modes of the on-board Zynq MPSoC

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The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes lanes for use by other mezzanine modules and expansion cards.

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MGT lanes should be listed separately, as they are more specific than just general I/Os.
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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors  A - F:

1. FMC A
2. FMC B
3. FMC C
4. FMC D
5. FMC E
6. FMC F
   

FMC A

FMC A Interfaces:

Table 3: FMC A connector interfaces

FMC A MGT Lanes:

Table 4: FMC A connector MGT lanes

FMC A Clock Signals:

Table 5: FMC A connector clock signal input

FMC A VCC/VCCIO:

Table 6: FMC A connector available VCC/VCCIO

FMC A Cooling Fan:

Table 7: FMC A connector cooling fan

FMC F

FMC F Interfaces:

Table 8: FMC F connector interface

FMC F MGT Lanes:

Table 9: FMC F connector MGT lanes

FMC F Clock Signals:

Table 10: FMC F connector clock signal input

FMC F VCC/VCCIO:

Table 11: FMC F connector available VCC/VCCIO

FMC F Cooling Fan:

Table 12: FMC F connector cooling fan

FMC B

FMC B Interfaces:

Table 13: FMC B connector interfaces

FMC B MGT Lanes:

Table 14: FMC B connector MGT lanes

FMC B Clock Signals:

Table 15: FMC B connector clock signal input

FMC B VCC/VCCIO:

Table 16: FMC B connector available VCC/VCCIO

FMC B Cooling Fan:

Table 17: FMC B connector cooling fan

FMC C

FMC C Interfaces:

Table 18: FMC C connector interfaces

FMC C MGT Lanes:

Table 19: FMC C connector MGT lanes

FMC C Clock Signals:

Table 20: FMC C connector clock signal input

FMC C VCC/VCCIO:

Table 21: FMC C connector available VCC/VCCIO

FMC C Cooling Fan:

Table 22: FMC C connector cooling fan

FMC D

FMC D Interfaces:

Table 23: FMC D connector interfaces

FMC D MGT Lanes:

Table 24: FMC D connector MGT lanes

FMC D Clock Signals:

Table 25: FMC D connector clock signal input

FMC D VCC/VCCIO:

Table 26: FMC D connector available VCC/VCCIO

FMC D Cooling Fan:

Table 27: FMC D connector cooling fan

FMC E

FMC E Interfaces:

Table 28: FMC E connector interfaces

FMC E MGT Lanes:

Table 29: FMC E connector MGT lanes

FMC E Clock Signals:

Table 30: FMC E connector clock signal input

FMC E VCC/VCCIO:

Table 31: FMC E connector available VCC/VCCIO

FMC E Cooling Fan:

Table 32: FMC E connector cooling fan

XMOD JTAG Interface

JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:

Signal Assignment of XMOD header J24 and J35

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The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 boardprogrammer.

XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.

XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.  J35 JTAG is used for FMC JTAG, is JTAGENB is low (see CPLD Firmware).

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:

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Following table describes the signals and control lines of the Gigabit Ethernet interface of the board:

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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

Table 40: DDR4 64-bit memory interface signals and pins

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.

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The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

Table 41: CAN interface signals and pins

SD Card Interface

The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:

The SD Card socket have following signal and pin assignment:

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Following table contains a brief description of the control signals of the fan connectors:

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Table 44: Clock generator Si5345A external interfaces

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.

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Table 46: MIO-pin assignment of the module's I²C interface

I²C addresses (7 bit without read/write-bit) for on-board slave devices are listed in the table below:

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The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have , the I²C interfaces of the EEPROM's are multiplexed to the I²C switch U37:

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Table 50: Reference clock signal oscillators

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Power distribution to the MPSoC PS and PL units:

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Power Rails

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Operating Temperature Ranges

The TEB0911 board is capable to be operated at an operational temperatur range of operational temperature range is 0 °C ... 85 °C without FMC cooling fans M1 ... M6 and NGFF M.2 PCIe socket U2.

Physical Dimensions

• Module Board size: ... mm 406mm × 234..30mm. mm.  Please download the assembly diagram for exact numbers.Mating height with standard connectors: ... mm.

• PCB thickness: 1... 65 mm.

• Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

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Revision History

Hardware Revision History

Table 65: Module hardware revision historyhistory

Hardware revision number can be found on the PCB board together with the board model number separated by the dash.

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Table 66: Document change history

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