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Overview

The Trenz Electronic TEB0911 UltraRack+ board is integrating a Xilinx Zynq UltraScale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SO-DIMM socket with 64-bit wide data bus, 22 MGT lanes and powerful switch-mode power supplies for all on-board voltages. The TEB0911 board exposes the pins of the Zynq MPSoC to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq UltraScale+ MPSoC and for developing purposes. The board is capable to be fitted to a enclosure, whereby on the enclosure's rear and front panel, I/O's, LVDS-pairs and MGT lanes are accessible through 6 on-board FMC connectors and other standard high-speed interfaces, namely USB3, SFP+, SSD, GbE, etc.

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Refer to http://trenz.org/teb0911-info for the current online version of this manual and other available documentation.

Key Features

• Zynq UltraScale+ MPSoC
  • ZU6,ZU9 or ZU15 on 1156 Pin Package
• 64bit DDR4 SODIMM (PS connected)
• M2 PCIe SSD (1-Lane)
• eMMC (bootable)
• Dual QSPI Flash (bootable)
• System Controller(LCMXO2-7000HC)
  • Power Sequencing
  • IO Expander
• Configurable PLLs
• GTH/GTP Reference CLKs

Front Panel

• 4 x FMC
  • 4 GTH per FMC
  • 68 ZynqMP PL IO per FMC
• DisplayPort (2-Lanes)
• RJ34 ETH + Dual USB3 Combo
• Dual Stack SFP+
• SD (bootable)
• Status LEDs

Back Panel

• 2 x FMC
  • 4/2 GTH
  • 12 ZynqMP PL IO per FMC
  • 56 SC IO per FMC
• USB JTAG/UART ZynqMP
• USB JTAG/GPIO FMC
• CAN FD (DB9 Connector)
• SMA (external CLK)
• 5polig 24V power connector

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Main Components

1. SFP+ 2x1 cage with integrated LED light pipes, J9
2. DisplayPort connector, J12
3. USB3 A 2x , RJ45 1x (stacked), J13
4. FMC connector (FMC B), J4
5. FMC B cooling fan, M2
6. FMC connector (FMC C), J8
7. FMC C cooling fan, M3
8. FMC connector (FMC D), J7
9. FMC D cooling fan, M4
10. FMC connector (FMC E), J6
11. FMC E cooling fan, M5
12. I²C programming header of on-board PLL clock generator U17, J22
13. 4-Wire PWM fan connector, J23
14. Main Power Jack 24V, J1
15. CAN bus D-SUB 9-pin male connector, J3
16. CAN bus 6-pin header male, J15
17. XMOD JTAG header for access to System Controller CPLD, J35
    
18. XMOD JTAG header for access to Zynq MPSoC, J24
19. 4-Wire PWM fan connector, J33
20. Battery Holder CR1220, B1
21. SMA coaxial connector (PLL Si5345A U17 clock input), J25
22. Push Button, S1
23. Push Button, S2
24. DDR4 SO-DIMM socket, U3
25. 4-bit DIP-switch, S4
26. 4-bit DIP-switch, S3
27. FMC connector (FMC A), J10
28. FMC A cooling fan, M1
29. FMC connector (FMC F), J21
30. FMC F cooling fan, M6
31. NGFF M.2 PCIe socket (Key M), U2
32. SD Card socket, J11
33. User LEDs (3x green, 1x red) with LED light pipe, D13 ... D16
    
34. Green LEDs dedicated to USB3 hub U4, D17 ... D19
35. Red LED indicating FPGAs 'DONE' signal, D6
36. 4-Wire PWM fan connector, J2
37. Xilinx Zynq Ultrascale+ MPSoC, U1
    

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:

Table 2: Available boot modes of the on-board Zynq MPSoC

Refer also to the documentation of the SC CPLD firmware of the TEB0911 board, section 'boot mode'.

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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FMC Connectors

The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT lanes for use by other mezzanine modules and expansion cards.

The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:

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Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors  A - F:

1. FMC A
2. FMC B
3. FMC C
4. FMC D
5. FMC E
6. FMC F
   

FMC A

FMC A Interfaces:

Table 3: FMC A connector interfaces

FMC A MGT Lanes:

Table 4: FMC A connector MGT lanes

FMC A Clock Signals:

Table 5: FMC A connector clock signal input

FMC A VCC/VCCIO:

Table 6: FMC A connector available VCC/VCCIO

FMC A Cooling Fan:

Table 7: FMC A connector cooling fan

FMC F

FMC F Interfaces:

Table 8: FMC F connector interface

FMC F MGT Lanes:

Table 9: FMC F connector MGT lanes

FMC F Clock Signals:

Table 10: FMC F connector clock signal input

FMC F VCC/VCCIO:

Table 11: FMC F connector available VCC/VCCIO

FMC F Cooling Fan:

Table 12: FMC F connector cooling fan

FMC B

FMC B Interfaces:

Table 13: FMC B connector interfaces

FMC B MGT Lanes:

Table 14: FMC B connector MGT lanes

FMC B Clock Signals:

Table 15: FMC B connector clock signal input

FMC B VCC/VCCIO:

Table 16: FMC B connector available VCC/VCCIO

FMC B Cooling Fan:

Table 17: FMC B connector cooling fan

FMC C

FMC C Interfaces:

Table 18: FMC C connector interfaces

FMC C MGT Lanes:

Table 19: FMC C connector MGT lanes

FMC C Clock Signals:

Table 20: FMC C connector clock signal input

FMC C VCC/VCCIO:

Table 21: FMC C connector available VCC/VCCIO

FMC C Cooling Fan:

Table 22: FMC C connector cooling fan

FMC D

FMC D Interfaces:

Table 23: FMC D connector interfaces

FMC D MGT Lanes:

Table 24: FMC D connector MGT lanes

FMC D Clock Signals:

Table 25: FMC D connector clock signal input

FMC D VCC/VCCIO:

Table 26: FMC D connector available VCC/VCCIO

FMC D Cooling Fan:

Table 27: FMC D connector cooling fan

FMC E

FMC E Interfaces:

Table 28: FMC E connector interfaces

FMC E MGT Lanes:

Table 29: FMC E connector MGT lanes

FMC E Clock Signals:

Table 30: FMC E connector clock signal input

FMC E VCC/VCCIO:

Table 31: FMC E connector available VCC/VCCIO

FMC E Cooling Fan:

Table 32: FMC E connector cooling fan

XMOD JTAG Interface

JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:

Signal Assignment of XMOD header J24 and J35

Table 33: XMOD interface signals

The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 programmer.

XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.

XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.  J35 JTAG is used for FMC JTAG, is JTAGENB is low (see CPLD Firmware).

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:

Table 34: XMOD adapter board DIP-switch positions for voltage configuration

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.

Following table describes the signals and control lines of the Gigabit Ethernet interface of the board:

Table 35: Ethernet PHY interface connections

USB3 Interface

On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.

The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

Table 36: USB3 signals and interfaces

SFP+ Interface

The TEB0911 board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) with data transmission rates up to 10 Gbit/s.

Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:

Table 37: SFP+ signals and interfaces

SSD Interface

On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.

Table 38: SSD signals and interfaces

DisplayPort Interface

The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.

Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

Table 39: DisplayPort signals and interfaces

DDR4 Memory Socket

On the TEB0911 board there is a DDR4 memory interface with a 64-bit databus width available for SO-DIMM modules.

Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

Table 40: DDR4 64-bit memory interface signals and pins

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.

CAN Interface

The TEB0911 board provides a CAN interface, the CAN transceiver is connected and operated by the SC CPLD:

The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

Table 41: CAN interface signals and pins

SD Card Interface

The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:

The SD Card socket have following signal and pin assignment:

Table 42: SD Card interface signals and connections

4-Wire PWM FAN Connectors

The TEB0911 offers 3x 4-wire PWM FAN connectors for optional cooling fans controlled by SC CPLD U27:

Following table contains a brief description of the control signals of the fan connectors:

Table 43: 4-wire PWM fan connectors signals and pins

PLL Clock Interfaces

The programmable 10-output reference clock generator U17 can be accessed through its I²C interface to be programed. The I²C interface is connected to the Zynq MPSoc via I²C switch U13 and to pin header J22.

With the SMA Coaxial connector J25 the clock generator can be supplied with an external clock signal.

Table 44: Clock generator Si5345A external interfaces

On-board Peripherals

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System Controller CPLD

The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27. The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.

The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO and PL pins. The signals of these pins are forwarded by the SC CPLD to control some of the on board peripherals.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins and singled ended PL pins:

For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.

The PS_1V8 and VCCINT_0V85 voltage levels are monitored by the voltage monitor circuit U89, which generates the POR_B signal to reset the board if voltage failure occurs. A manual reset is also possible by driving the pin 'MR' on SC CPLD, bank 4, pin L7 to GND. Refer to documentation of the SC CPLD firmware for detailed information to reset the board manually.

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High-speed USB2 ULPI PHY

USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U16.

Table 45: USB PHY interface connections

4-port USB3 Hub

On the TEB0911 board there are to 2 USB3 Super Speed ports available, which are also downward compatible to USB2 High Speed ports. The USB3 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3 Hub controller U4. The pin-strap configuration option of the USB3 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller are also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U37.

On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3 data lane. For the USB2 interface, the controller is connected to the on-board USB2 PHY U15. The USB2 PHY is connected via ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.

The USB3 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U27, bank 4, pin K2.

8-Channel I²C Switches

All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.

For this purpose, the TEB0911 board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.

Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.

The on-board I²C bus works with reference voltage 3.3V, it is connected to the MPSoC I²C interface via PS MIO bank (pins MIO38, MIO39) and configured as master.

Table 46: MIO-pin assignment of the module's I²C interface

I²C addresses (7 bit without read/write-bit) for on-board slave devices are listed in the table below:

Table 46:  On-board peripherals' I²C-interfaces device slave addresses

Configuration EEPROMs

The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip, the I²C interfaces of the EEPROM's are multiplexed to the I²C switch U37:

Table 47:  On-board configuration EEPROMs overview

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver U48 is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

The transceiver is connected to System Controller CPLD U27, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD.

On-board Flash Memory

On-board QSPI flash memory U24 and U25 on the TEB0911 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

The TEB0911 board is also equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

Table 48:  On-board Flash memory ICs overview

Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.

Table 49:  PS MIO pin assignment of the Flash memory ICs

Oscillators

The TEB0911 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Table 50: Reference clock signal oscillators

Programmable Clock Generator Si5338A

There is a Si5338A U12, Silicon Labs I²C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.

Table 51: Programmable quad PLL clock generator inputs and outputs

Programmable Clock Generator Si5345A

Following table shows on-board Silicon Labs I²C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

Table 52: Programmable 10-output PLL clock generator inputs and outputs

On-board LEDs

The TEB0911 board is equipped with several LEDs to signal current states and activities.

Table 53: On-board LEDs

User Buttons

There are two switch buttons available to the user connected to the SC CPLD U27:

Table 54: On-board switch buttons

Configuration DIP-switches

There are two 4-bit DIP-witches S3 and S4 present on the TEB0911 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:

Table 55: DIP-switch S3 and S4 functionality description

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of the board mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 56: Typical power consumption, *to Be Determined soon with reference design setup.

Power supply with minimum current capability of 2A for system startup is recommended. If using all FMC connectors with FPGA Mezzanine Cards, a higher current availability of up to 4A is recommended.

The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.

This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.

The Processing System contains three Power Domains:

• Battery Power Domain (BBRAM and RTC)
• Full-Power Domain (Application Processing Unit, DDR Controller, Graphics Processing Unit and High-Speed Connectivity)
• Low-Power Domain (Real-Time Processing Unit, Security and Configuration Unit, Platform Management Unit, System Monitor and General Connectivity)
• Programmable Logic (PL)

Power Distribution Dependencies

There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Power distribution to the MPSoC PS and PL units:

Power-On Sequence

The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.

On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:

1. Low-Power Domain (LPD)
2. Programmable Logic (PL) and Full-Power Domain (FPD)
3. GTH, PS GTR transceiver and DDR memory

Hence, those three power instances will be powered up consecutively when the Power-Good signals of the previous instance is asserted.

Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

Power Rails

Table 57: Power pin description of peripherals' connectors

Table 58: Power pin description of XMOD/JTAG Connector

Table 59: Power pin description of main power supply connector

Table 60: Power pin description of FMC connectors

Table 61: Power pin description of FAN connectors

Bank Voltages

Table 62: Zynq MPSoC PS/PL VCCO bank voltages

Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 63: Module absolute maximum ratings

Recommended Operating Conditions

Table 64: Module recommended operating conditions

Operating Temperature Ranges

The TEB0911 board operational temperature range is 0 °C ... 85 °C without FMC cooling fans M1 ... M6 and NGFF M.2 PCIe socket U2.

Physical Dimensions

• Board size: 406mm × 234.30mm.  Please download the assembly diagram for exact numbers.

• PCB thickness: 1.65 mm.

• Please download the step model for exact numbers.

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Table 65: Module hardware revision history

Hardware revision number can be found on the PCB board together with the board model number separated by the dash.

Document Change History

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Table 66: Document change history

Disclaimer

02 Sept 2017