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The Trenz Electronic TEB0911 UltraRack+ board is integrating a Xilinx Zynq UltrascaleUltraScale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SO-DIMM socket with 64-bit wide data bus, 22 MGT lanes and powerful switch-mode power supplies for all on-board voltages. . The TEB0911 board exposes the pins of the Zynq MPSoC to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq UltrascaleUltraScale+ MPSoC and for developing purposes. The board is capable to be fitted to a enclosure, whereby on the enclosure's rear and front panel, I/O's, LVDS-pairs and MGT lanes are accessible through 6 on-board FMC connectors and other standard high-speed interfaces, namely USB3, SFP+, SSD, GbE, etc.

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titleFigure 1: TEB0911-03 block diagram


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Main Components

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titleFigure 2: TEB0911-03 main components


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  1. SFP+ 2x1 cage with integrated LED light pipes, J9
  2. DisplayPort connector, J12
  3. USB3 A 2x , RJ45 1x (stacked), J13
  4. FMC connector (FMC B), J4
  5. FMC B cooling fan, M2
  6. FMC connector (FMC C), J8
  7. FMC C cooling fan, M3
  8. FMC connector (FMC D), J7
  9. FMC D cooling fan, M4
  10. FMC connector (FMC E), J6
  11. FMC E cooling fan, M5
  12. I²C programming header of on-board PLL clock generator U17, J22
  13. 4-Wire PWM fan connector, J23
  14. Main Power Jack 24V, J1
  15. CAN bus D-SUB 9-pin male connector, J3
  16. CAN bus 6-pin header male, J15
  17. XMOD JTAG header for access to System Controller CPLD, J35
  18. XMOD JTAG header for access to Zynq MPSoC, J24
  19. 4-Wire PWM fan connector, J33
  20. Battery Holder CR1220, B1
  21. SMA coaxial connector (PLL Si5345A U17 clock input), J25
  22. Push Button, S1
  23. Push Button, S2
  24. DDR4 SO-DIMM socket, U3
  25. 4-bit DIP-switch, S4
  26. 4-bit DIP-switch, S3
  27. FMC connector (FMC A), J10
  28. FMC A cooling fan, M1
  29. FMC connector (FMC F), J21
  30. FMC F cooling fan, M6
  31. NGFF M.2 PCIe socket (Key M), U2
  32. SD Card socket, J11
  33. User LEDs (3x green, 1x red) with LED light pipe, D13 ... D16
  34. Green LEDs dedicated to USB3 hub U4, D17 ... D19
  35. Red LED indicating FPGAs 'DONE' signal, D6
  36. 4-Wire PWM fan connector, J2
  37. Xilinx Zynq Ultrascale+ MPSoC, U1

Initial Delivery State

Storage device name

Content

Notes

User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)EmptyNot programmed
USB3 HUB Configuration EEPROM (Microchip 24LC128-I/ST)EmptyNot programmed
Si5338A programmable PLL NVM OTPEmptyNot programmed
Si5345A programmable PLL NVM OTPEmptyNot programmed
eMMC Flash memoryEmptyNot programmed
2x QSPI Flash memoryEmptyNot programmed

...

HTML
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
  -->

 

Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors  A - F:

  1. FMC A
  2. FMC B
  3. FMC C
  4. FMC D
  5. FMC E
  6. FMC F

 

Anchor
FMC A
FMC A

 

FMC A

FMC A Interfaces:

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J10

(FMC A)





I/O126Bank 44 HDFMCAF_1V8-
5628SC CPLD U27 Bank 1FMCAF_1V8-
I²C2-I²C-Switch U37-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 128 GTH-4x MGT lanes
Clock Input-1Bank 128 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 03.3VSB

'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'

Table 3: FMC A connector interfaces

FMC A MGT Lanes:

FMCMGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin

J10

(FMC A)


0128GTH
  • B128_RX0_P
  • B128_RX0_N
  • B128_TX0_P
  • B128_TX0_N

J10-C6
J10-C7
J10-C2
J10-C3

MGTHRXP0_128, T33
MGTHRXN0_128, T34
MGTHTXP0_128, T29
MGTHTXN0_128, T30

1128GTH
  • B128_RX1_P
  • B128_RX1_N
  • B128_TX1_P
  • B128_TX1_N

J10-A2
J10-A3
J10-A22
J10-A23

MGTHRXP1_128, P33
MGTHRXN1_128, P34
MGTHTXP1_128, R31
MGTHTXN1_128, R32

2128GTH
  • B128_RX2_P
  • B128_RX2_N
  • B128_TX2_P
  • B128_TX2_N

J10-A6
J10-A7
J10-A26
J10-A27

MGTHRXP2_128, N31
MGTHRXN2_128, N32
MGTHTXP2_128, P29
MGTHTXN2_128, P30

3128GTH
  • B128_RX3_P
  • B128_RX3_N
  • B128_TX3_P
  • B128_TX3_N

J10-A10
J10-A11
J10-A30
J10-A31

MGTHRXP3_128, M33
MGTHRXN3_128, M34
MGTHTXP3_128, M29
MGTHTXN3_128, M30

Table 4: FMC A connector MGT lanes

FMC A Clock Signals:

FMCSignal Schematic NameBankFMC Connector PinFPGA PinNotes

J10

(FMC A)

  • B128_CLK0_P
  • B128_CLK0_N
128

J10-D4
J10-D5

MGTREFCLK0P_128, R27
MGTREFCLK0N_128, R28

Supplied by attached module

Table 5: FMC A connector clock signal input

FMC A VCC/VCCIO:

FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J10

(FMC A)

FMCA_3V3

J10-D36
J10-D38
J10-D40
J10-C39

DCDC U32,
max. cur.: 5A

Enable by SC CPLD U27, bank 2, pin Y18
Signal: 'EN_A_3V3'

3V3SB

J10-D32

DCDC U50,

max. cur.: 1A
not dedicated for FMC connectors
12V_FMC_AF

J10-C35
J10-C37

DCDC U51,
max. cur.: 5A

-
FMCAF_1V8

J10-H40
J10-G39
J10-F40
J10-E39

DCDC U39,
max. cur.: 5A

Enable by SC CPLD U27, bank 2, pin W19
Signal: 'EN_AF_1V8'

Table 6: FMC A connector available VCC/VCCIO

FMC A Cooling Fan:

FMCFan DesignatorEnable SignalNotes

J10

(FMC A)

M1

Enable by SC CPLD U27, bank 2, pin Y19
Signal: 'FAN_A_EN'

-

Table 7: FMC A connector cooling fan

Anchor
FMC F
FMC F

 

FMC F

FMC F Interfaces:

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J21

(FMC F)








I/O

126Bank 44 HDFMCAF_1V8-
2814SC CPLD U27 Bank 1FMCAF_1V8-
2814SC CPLD U27 Bank 3FMCAF_1V8-
I²C2-I²C-Switch U37-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-4 (2 x RX/TX)Bank 129 GTH-2x MGT lanes
Clock Input-1Bank 129 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'

Table 8: FMC F connector interface

FMC F MGT Lanes:

FMCMGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin

J21

(FMC F)


0129GTH
  • B129_RX0_P
  • B129_RX0_N
  • B129_TX0_P
  • B129_TX0_N

J21-C6
J21-C7
J21-C2
J21-C3

MGTHRXP0_129, L31
MGTHRXN0_129, L32
MGTHTXP0_129, K29
MGTHTXN0_129, K30

1129GTH
  • B129_RX1_P
  • B129_RX1_N
  • B129_TX1_P
  • B129_TX1_N

J21-A2
J21-A3
J21-A22
J21-A23

MGTHRXP1_129, K33
MGTHRXN1_129, K34
MGTHTXP1_129, J31
MGTHTXN1_129, J32

Table 9: FMC F connector MGT lanes

FMC F Clock Signals:

FMCSignal Schematic NameBankFMC Connector PinFPGA PinNotes

J21

(FMC F)

  • B129_CLK0_P
  • B129_CLK0_N
129

J21-D4
J21-D5

MGTREFCLK0P_129, L27
MGTREFCLK0N_129, L28

Supplied by attached module

Table 10: FMC F connector clock signal input

FMC F VCC/VCCIO:

FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J21

(FMC F)

FMCF_3V3

J21-D36
J21-D38
J21-D40
J21-C39

DCDC U42,
max. cur.: 5A

Enable by SC CPLD U27, bank 2, pin Y10
Signal: 'EN_F_3V3'

3V3SB

J21-D32

DCDC U50,

max. cur.: 1A
not dedicated for FMC connectors
12V_FMC_AF

J21-C35
J21-C37

DCDC U51,
max. cur.: 5A

-
FMCAF_1V8

J21-H40
J21-G39
J21-F40
J21-E39

DCDC U39,
max. cur.: 5A

Enable by SC CPLD U27, bank 2, pin W19
Signal: 'EN_AF_1V8'

Table 11: FMC F connector available VCC/VCCIO

FMC F Cooling Fan:

FMCFan DesignatorEnable SignalNotes

J21

(FMC F)

M6

Enable by SC CPLD U27, bank 2, pin W18
Signal: 'FAN_F_EN'

-

Table 12: FMC F connector cooling fan

Anchor
FMC B
FMC B

 

FMC B

FMC B Interfaces:

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J4

(FMC B)









I/O

2412Bank 47 HDFMCBC_1V8-
2010Bank 48 HDFMCBC_1V8-
2412Bank 49 HDFMCBC_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 03.3VSB-
MGT-8 (4 x RX/TX)Bank 130 GTH-4x MGT lanes
Clock Input-2Bank 48 HD-

2x Reference clock inputs to PL bank

-1Bank 130 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 03.3VSB

'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

Table 13: FMC B connector interfaces

FMC B MGT Lanes:

FMCMGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin

J4

(FMC B)


3130GTH
  • B130_RX3_P
  • B130_RX3_N
  • B130_TX3_P
  • B130_TX3_N

J4-C6
J4-C7
J4-C2
J4-C3

MGTHRXP3_130, B33
MGTHRXN3_130, B34
MGTHTXP3_130, A31
MGTHTXN3_130, A32

2130GTH
  • B130_RX2_P
  • B130_RX2_N
  • B130_TX2_P
  • B130_TX2_N

J4-A2
J4-A3
J4-A22
J4-A23

MGTHRXP2_130, C31
MGTHRXN2_130, C32
MGTHTXP2_130, B29
MGTHTXN2_130, B30

1130GTH
  • B130_RX1_P
  • B130_RX1_N
  • B130_TX1_P
  • B130_TX1_N

J4-A6
J4-A7
J4-A26
J4-A27

MGTHRXP1_130, D33
MGTHRXN1_130, D34
MGTHTXP1_130, D29
MGTHTXN1_130, D30

0130GTH
  • B130_RX0_P
  • B130_RX0_N
  • B130_TX0_P
  • B130_TX0_N

J4-A10
J4-A11
J4-A30
J4-A31

MGTHRXP0_130, E31
MGTHRXN0_130, E32
MGTHTXP0_130, F29
MGTHTXN0_130, F30

Table 14: FMC B connector MGT lanes

FMC B Clock Signals:

FMCSignal Schematic NameBankFMC Connector PinFPGA PinNotes

J4

(FMC B)



  • B130_CLK0_P
  • B130_CLK0_N
130

J4-D4
J4-D5

MGTREFCLK0P_130, G27
MGTREFCLK0N_130, G28

Supplied by attached module
  • B_CLK0_M2C_P
  • B_CLK0_M2C_N
48 HD

J4-H4
J4-H5

IO_L6P_HDGC_48, F17
IO_L6N_HDGC_48, F18

Supplied by attached module
  • B_CLK1_M2C_P
  • B_CLK1_M2C_N
48 HD

J4-G2
J4-G3

IO_L5P_HDGC_48, G18
IO_L5N_HDGC_48, G19

Supplied by attached module

Table 15: FMC B connector clock signal input

FMC B VCC/VCCIO:

FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J4

(FMC B)

FMCB_3V3

J4-D36
J4-D38
J4-D40
J4-C39

DCDC U33,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin G11
Signal: 'EN_B_3V3'

3V3SB

J4-D32

DCDC U50,

max. cur.: 1A
not dedicated for FMC connectors
12V

J4-C35
J4-C37

DCDC U82,
max. cur.: 8A

not dedicated for FMC connectors

FMCBC_1V8

J4-H40
J4-G39
J4-F40
J4-E39

DCDC U40,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin A3
Signal: 'EN_BC_1V8'

Table 16: FMC B connector available VCC/VCCIO

FMC B Cooling Fan:

FMCFan DesignatorEnable SignalNotes

J4

(FMC B)

M2

Enable by SC CPLD U27, bank 0, pin A2
Signal: 'FAN_B_EN'

-

Table 17: FMC B connector cooling fan

Anchor
FMC C
FMC C

 

FMC C

FMC C Interfaces:

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J8

(FMC C)

I/O2010Bank 50 HDFMCBC_1V8-
68483424Bank 67 HPFMCBC_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 230 GTH-4x MGT lanes
Clock Input-2Bank 50 HD-

2x Reference clock inputs to PL bank

-1Bank 230 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'

Table 18: FMC C connector interfaces

FMC C MGT Lanes:

FMCMGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin

J8

(FMC C)

3230GTH
  • B230_RX3_P
  • B230_RX3_N
  • B230_TX3_P
  • B230_TX3_N

J8-C6
J8-C7
J8-C2
J8-C3

MGTHRXP3_230, A4
MGTHRXN3_230, A3
MGTHTXP3_230, A8
MGTHTXN3_230, A7

2230GTH
  • B230_RX2_P
  • B230_RX2_N
  • B230_TX2_P
  • B230_TX2_N

J8-A2
J8-A3
J8-A22
J8-A23

MGTHRXP2_230, B2
MGTHRXN2_230, B1
MGTHTXP2_230, B6
MGTHTXN2_230, B5

1230GTH
  • B230_RX1_P
  • B230_RX1_N
  • B230_TX1_P
  • B230_TX1_N

J8-A6
J8-A7
J8-A26
J8-A27

MGTHRXP1_230, C4
MGTHRXN1_230, C3
MGTHTXP1_230, D6
MGTHTXN1_230, D5

0230GTH
  • B230_RX0_P
  • B230_RX0_N
  • B230_TX0_P
  • B230_TX0_N

J8-A10
J8-A11
J8-A30
J8-A31

MGTHRXP0_230, D2
MGTHRXN0_230, D1
MGTHTXP0_230, E4
MGTHTXN0_230, E3

Table 19: FMC C connector MGT lanes

FMC C Clock Signals:

FMCSignal Schematic NameBankFMC Connector PinFPGA PinNotes

J8

(FMC C)



  • B230_CLK0_P
  • B230_CLK0_N
230

J8-D4
J8-D5

MGTREFCLK0P_230, C8
MGTREFCLK0N_230, C7

Supplied by attached module
  • C_CLK0_M2C_P
  • C_CLK0_M2C_N
50 HD

J8-H4
J8-H5

IO_L7P_HDGC_50, J12
IO_L7N_HDGC_50, H12

Supplied by attached module
  • C_CLK1_M2C_P
  • C_CLK1_M2C_N
50 HD

J8-G2
J8-G3

IO_L8P_HDGC_50, H13
IO_L8N_HDGC_50, G13

Supplied by attached module

Table 20: FMC C connector clock signal input

FMC C VCC/VCCIO:

FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J8

(FMC C)

FMCC_3V3

J8-D36
J8-D38
J8-D40
J8-C39

DCDC U34,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin E11
Signal: 'EN_C_3V3'

3V3SB

J8-D32

DCDC U50,

max. cur.: 1A
not dedicated for FMC connectors
12V

J8-C35
J8-C37

DCDC U82,
max. cur.: 8A

not dedicated for FMC connectors

FMCBC_1V8

J8-H40
J8-G39
J8-F40
J8-E39

DCDC U40,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin A3
Signal: 'EN_BC_1V8'

Table 21: FMC C connector available VCC/VCCIO

FMC C Cooling Fan:

FMCFan DesignatorEnable SignalNotes

J8

(FMC C)

M3

Enable by SC CPLD U27, bank 0, pin B3
Signal: 'FAN_C_EN'

-

Table 22: FMC C connector cooling fan

Anchor
FMC D
FMC D

 

FMC D

FMC D Interfaces:

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J7

(FMC D)








I/O2010Bank 65 HPFMCDE_1V8-
4824Bank 66 HPFMCDE_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 229 GTH-4x MGT lanes
Clock Input-2Bank 65 HP-

2x Reference clock inputs to PL bank

-1Bank 229 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

Table 23: FMC D connector interfaces

FMC D MGT Lanes:

FMCMGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin

J7

(FMC D)


3229GTH
  • B229_RX3_P
  • B229_RX3_N
  • B229_TX3_P
  • B229_TX3_N

J7-C6
J7-C7
J7-C2
J7-C3

MGTHRXP3_229, F2
MGTHRXN3_229, F1
MGTHTXP3_229, F6
MGTHTXN3_229, F5

2229GTH
  • B229_RX2_P
  • B229_RX2_N
  • B229_TX2_P
  • B229_TX2_N

J7-A2
J7-A3
J7-A22
J7-A23

MGTHRXP2_229, H2
MGTHRXN2_229, H1
MGTHTXP2_229, G4
MGTHTXN2_229, G3

1229GTH
  • B229_RX1_P
  • B229_RX1_N
  • B229_TX1_P
  • B229_TX1_N

J7-A6
J7-A7
J7-A26
J7-A27

MGTHRXP1_229, J4
MGTHRXN1_229, J3
MGTHTXP1_229, H6
MGTHTXN1_229, H5

0229GTH
  • B229_RX0_P
  • B229_RX0_N
  • B229_TX0_P
  • B229_TX0_N

J7-A10
J7-A11
J7-A30
J7-A31

MGTHRXP0_229, K2
MGTHRXN0_229, K1
MGTHTXP0_229, K6
MGTHTXN0_229, K5

Table 24: FMC D connector MGT lanes

FMC D Clock Signals:

FMCSignal Schematic NameBankFMC Connector PinFPGA PinNotes

J7

(FMC D)

  • B229_CLK0_P
  • B229_CLK0_N
229

J7-D4
J7-D5

MGTREFCLK0P_229, G8
MGTREFCLK0N_229, G7

Supplied by attached module
  • D_CLK0_M2C_P
  • D_CLK0_M2C_N
65 HP

J7-H4
J7-H5

IO_L14P_T2L_N2_GC_65, AG5
IO_L14N_T2L_N3_GC_65, AG4

Supplied by attached module
  • D_CLK1_M2C_P
  • D_CLK1_M2C_N
65 HP

J7-G2
J7-G3

IO_L13P_T2L_N0_GC_QBC_65, AE5
IO_L13N_T2L_N1_GC_QBC_65, AF5

Supplied by attached module

Table 25: FMC D connector clock signal input

FMC D VCC/VCCIO:

FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J7

(FMC D)

FMCD_3V3

J7-D36
J7-D38
J7-D40
J7-C39

DCDC U35,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin F8
Signal: 'EN_D_3V3'

3V3SB

J7-D32

DCDC U50,

max. cur.: 1A
not dedicated for FMC connectors
12V

J7-C35
J7-C37

DCDC U82,
max. cur.: 8A

not dedicated for FMC connectors

FMCDE_1V8

J7-H40
J7-G39
J7-F40
J7-E39

DCDC U41,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin C5
Signal: 'EN_DE_1V8'

Table 26: FMC D connector available VCC/VCCIO

FMC D Cooling Fan:

FMCFan DesignatorEnable SignalNotes

J7

(FMC D)

M4

Enable by SC CPLD U27, bank 0, pin D7
Signal: 'FAN_D_EN'

-

Table 27: FMC D connector cooling fan

Anchor
FMC E
FMC E

 

FMC E

FMC E Interfaces:

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J6

(FMC E)









I/O2412Bank 65 HPFMCDE_1V8-
4422Bank 64 HPFMCDE_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 228 GTH-4x MGT lanes
Clock Input-2Bank 64 HP-

2x Reference clock inputs to PL bank

-1Bank 228 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

Table 28: FMC E connector interfaces

FMC E MGT Lanes:

FMCMGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin

J6

(FMC E)


3228GTH
  • B228_RX3_P
  • B228_RX3_N
  • B228_TX3_P
  • B228_TX3_N

J6-C6
J6-C7
J6-C2
J6-C3

MGTHRXP3_228, L4
MGTHRXN3_228, L3
MGTHTXP3_228, M6
MGTHTXN3_228, M5

2228GTH
  • B228_RX2_P
  • B228_RX2_N
  • B228_TX2_P
  • B228_TX2_N

J6-A2
J6-A3
J6-A22
J6-A23

MGTHRXP2_228, M2
MGTHRXN2_228, M1
MGTHTXP2_228, N4
MGTHTXN2_228, N3

1228GTH
  • B228_RX1_P
  • B228_RX1_N
  • B228_TX1_P
  • B228_TX1_N

J6-A6
J6-A7
J6-A26
J6-A27

MGTHRXP1_228, P2
MGTHRXN1_228, P1
MGTHTXP1_228, P6
MGTHTXN1_228, P5

0228GTH
  • B228_RX0_P
  • B228_RX0_N
  • B228_TX0_P
  • B228_TX0_N

J6-A10
J6-A11
J6-A30
J6-A31

MGTHRXP0_228, T2
MGTHRXN0_228, T1
MGTHTXP0_228, R4
MGTHTXN0_228, R3

Table 29: FMC E connector MGT lanes

FMC E Clock Signals:

FMCSignal Schematic NameBankFMC Connector PinFPGA PinNotes

J6

(FMC E)

  • B228_CLK0_P
  • B228_CLK0_N
228

J6-D4
J6-D5

MGTREFCLK0P_228, L8
MGTREFCLK0N_228, L7

Supplied by attached module
  • E_CLK0_M2C_P
  • E_CLK0_M2C_N
64 HP

J6-H4
J6-H5

IO_L12P_T1U_N10_GC_64, AL8
IO_L12N_T1U_N11_GC_64, AL7

Supplied by attached module
  • E_CLK1_M2C_P
  • E_CLK1_M2C_N
64 HP

J6-G2
J6-G3

IO_L11P_T1U_N8_GC_64, AK8
IO_L11N_T1U_N9_GC_64, AK7

Supplied by attached module

Table 30: FMC E connector clock signal input

FMC E VCC/VCCIO:

FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J6

(FMC E)

FMCE_3V3

J6-D36
J6-D38
J6-D40
J6-C39

DCDC U36,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin E8
Signal: 'EN_E_3V3'

3V3SB

J6-D32

DCDC U50,

max. cur.: 1A
not dedicated for FMC connectors
12V

J6-C35
J6-C37

DCDC U82,
max. cur.: 8A

not dedicated for FMC connectors

FMCDE_1V8

J6-H40
J6-G39
J6-F40
J6-E39

DCDC U41,
max. cur.: 5A

Enable by SC CPLD U27, bank 0, pin C5
Signal: 'EN_DE_1V8'

Table 31: FMC E connector available VCC/VCCIO

FMC E Cooling Fan:

FMCFan DesignatorEnable SignalNotes

J6

(FMC E)

M5

Enable by SC CPLD U27, bank 0, pin D6
Signal: 'FAN_E_EN'

-

Table 32: FMC E connector cooling fan

XMOD JTAG Interface

JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35:

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titleFigure 4: XMOD header J24 and J35


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Signal Assignment of XMOD header J24 and J35

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titleFigure 6: USB3 interface


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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

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titleFigure 7: SFP+ interface


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ConnectorInterface

Signal Schematic Name

Connected toLogicNotes

SFP+ J9A

MGT Lane
  • B129_TX3_P
  • B129_TX3_N
  • B129_RX3_P
  • B129_RX3_N

MGTHTXP3_129, G31
MGTHTXN3_129, G32
MGTHRXP3_129, F33
MGTHRXN3_129, F34

TX: Output

RX: Input

Multi gigabit highspeed
data lane
I²C
  • SFP0_SDA
  • SFP0_SCL
8-channel I²C-switch U37BiDir2-wire Serial Interface
Control Lines
  • SFP0_RS0
I²C 8-bit I/O Port-Expander U86

Output, low active

Full RX bandwidth
  • SFP0_RS1
Output, low activeReduced RX bandwidth
  • SFP0_M-DEF0
Input, low activeModule present / not present
  • SFP0_TX_FAULT
Input, high activeFault / Normal Operation
  • SFP0_LOS
SC CPLD U27, bank 2, pin V8Input, high activeLoss of receiver signal
  • SFP0_TX_DIS
SC CPLD U27, bank 2, pin Y7Output, low activeSFP Enabled / Disabled

SFP+ J9B

MGT Lane
  • B129_TX2_P
  • B129_TX2_N
  • B129_RX2_P
  • B129_RX2_N

MGTHTXP2_129, H29
MGTHTXN2_129, H30
MGTHRXP2_129, H33
MGTHRXN2_129, H34

TX: Output

RX: Input

Multi gigabit highspeed
data lane

I²C
  • SFP1_SDA
  • SFP1_SCL
8-channel I²C-switch U37Bidir2-wire Serial Interface
Control Lines
  • SFP1_RS0
I²C 8-bit I/O Port-Expander U86Output, low activeFull RX bandwidth
  • SFP1_RS1
Output, low activeReduced RX bandwidth
  • SFP1_M-DEF0
Input, low activeModule present / not present
  • SFP1_TX_FAULT
Input, high activeFault / Normal Operation
  • SFP1_LOS
SC CPLD U27, bank 2, pin W7Input, high activeLoss of receiver signal
  • SFP1_TX_DIS
SC CPLD U27, bank 2, pin V7Output. low activeSFP Enabled / Disabled

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titleFigure 8: SSD interface


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ConnectorInterface

Signal Schematic Name

Connected toNotes

M.2-NGFF

PCIe Socket

U2

MGT Lane
  • B505_TX0_P
  • B505_TX0_N
  • B505_RX0_P
  • B505_RX0_N

PS_MGTRTXP0_505, AB29
PS_MGTRTXN0_505, AB30
PS_MGTRRXP0_505, AB33
PS_MGTRTXN0_505, AB34

Multi gigabit highspeed
data lane

TX: Output

RX: Input

Clock Input
  • SSD_RCLK_P
  • SSD_RCLK_N
Quad programmable PLL clock
generator U12, CLK0
Reference clock signal
Control Lines
  • SSD1_LED
SC CPLD U27, bank 2, pin AA13LED, Output, High active
  • SSD1_SLEEP
SC CPLD U27, bank 2, pin AA12PCIe sleep state, Input, Low active
  • SSD1_PERSTN
SC CPLD U27, bank 2, pin AA11PCIe reset, Input, Low active
  • SSD1_WAKE
SC CPLD U27, bank 2, pin AB11PCIe Link reactivation, Input, Low active
  • SSD1_CLKRQ
connect to GNDPCIe Clock Request, Low active

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titleFigure 9: DisplayPort interface


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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

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titleFigure 10: DDR4 memory interface


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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

ConnectorDDR4 SDRAM I/O Signal

Signal Schematic Name

Connected toNotes

DDR4 SO-DIMM

Socket U13

Address inputs
  • DDR4-A0 ... DDR4-A16
PS DDR Bank 504-
Bank address inputs
  • DDR4-BA0 / DDR4-BA1
-
Bank group inputs
  • DDR4-BG0 / DDR4-BG1
-
Differential clocks
  • DDR4-CLK0_P
  • DDR4-CLK0_N
  • DDR4-CLK1_P
  • DDR4-CLK1_N
2 x DDR4 clock
Data input/output
  • DQ0 ... DQ63
-
Check bit input/output
  • CB0 ... CB7
-
Data strobe (differential)
  • DDR4-DQS0_P
  • DDR4-DQS0_N
  • ...
  • DDR4-DQS8_P
  • DDR4-DQS8_N
-
Data mask and data bus inversion
  • DDR4-DM0 ... DDR4-DM8
-
Serial address inputs
  • DDR4-SA0 ...  DDR4-SA2

address range configuration on I²C bus

Control Signals
  • DDR4-CS_N0 / DDR4-CS_N1
chip selest signal
  • DDR4-ODT0 / DDR4-ODT1
On-die termination enable
  • DDR4-RESET
nRESET
  • DDR4-PAR
Command and address parity input
  • DDR4-CKE0 / DDR4-CKE1
Clock enable
  • DDR4-ALERT
CRC error flag
  • DDR4-ACT
Activation command input
  • DDR4-EVENT
Temperature event
I²C
  • DDR4-SCL
  • DDR4-SDA
8-channel I²C
switch U37
-

Table 40: DDR4 64-bit memory interface signals and pins

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.

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titleFigure 11: CAN interface


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The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

ConnectorSignal Schematic NameConnected toNotes

D-SUB 9-pin
male connector

J3

  • CAN_H
CAN Transceiver U48, pin 7-
  • CAN_L
CAN Transceiver U48, pin 6-

6-pin male header

J15

  • CAN_H
CAN Transceiver U48, pin 7-
  • CAN_L
CAN Transceiver U48, pin 6-
CAN TransceiverSignal Schematic NameConnected toNotes
TCAN337 U48
  • CAN_TX
SC CPLD U27, bank 0, pin C163.3V VCCIO
  • CAN_RX
SC CPLD U27, bank 0, pin B153.3V VCCIO
  • CAN_S
SC CPLD U27, bank 0, pin C153.3V VCCIO
  • CAN_FAULT
SC CPLD U27, bank 0, pin D153.3V VCCIO

Table 41: CAN interface signals and pins

SD Card Interface

The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:

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titleFigure 12: SD Card interface


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The SD Card socket have following signal and pin assignment:

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titleFigure 14: PLL clock interface


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ConnectorSignal Schematic NameConnected toNotes

Pin Header

J22

  • PLL_SCL
clock generator U17, pin 16PS_1V8 VCCIO

  • PLL_SDA
clock generator U17, pin 18

SMA Coax

J25

  • CLK_PLL_IN
clock generator U17, pin 1-

Table 44: Clock generator Si5345A external interfaces

On-board Peripherals

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Table 65: Module hardware revision history

 

Hardware revision number can be found on the PCB board together with the board model number separated by the dash.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • Figure 1: fixed Zynq to FMC IO count to 148
2019-08-27v.184John Hartfiel
  • typo
2019-05-10v.183John Hartfiel
  • correction of J8 Pin count description
2018-07-23v.182Ali Naseri
  • Initial document
--all

Page info
infoTypeModified users
typeFlat
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Table 66: Document change history

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