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anchor	Figure_1
title	Figure 1: TEB0911-03 block diagram

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Main Components

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anchor	Figure_2
title	Figure 2: TEB0911-03 main components

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SFP+ 2x1 cage with integrated LED light pipes, J9
DisplayPort connector, J12
USB3 A 2x , RJ45 1x (stacked), J13
FMC connector (FMC B), J4
FMC B cooling fan, M2
FMC connector (FMC C), J8
FMC C cooling fan, M3
FMC connector (FMC D), J7
FMC D cooling fan, M4
FMC connector (FMC E), J6
FMC E cooling fan, M5
I²C programming header of on-board PLL clock generator U17, J22
4-Wire PWM fan connector, J23
Main Power Jack 24V, J1
CAN bus D-SUB 9-pin male connector, J3
CAN bus 6-pin header male, J15
XMOD JTAG header for access to System Controller CPLD, J35
XMOD JTAG header for access to Zynq MPSoC, J24
4-Wire PWM fan connector, J33
Battery Holder CR1220, B1
SMA coaxial connector (PLL Si5345A U17 clock input), J25
Push Button, S1
Push Button, S2
DDR4 SO-DIMM socket, U3
4-bit DIP-switch, S4
4-bit DIP-switch, S3
FMC connector (FMC A), J10
FMC A cooling fan, M1
FMC connector (FMC F), J21
FMC F cooling fan, M6
NGFF M.2 PCIe socket (Key M), U2
SD Card socket, J11
User LEDs (3x green, 1x red) with LED light pipe, D13 ... D16
Green LEDs dedicated to USB3 hub U4, D17 ... D19
Red LED indicating FPGAs 'DONE' signal, D6
4-Wire PWM fan connector, J2
Xilinx Zynq Ultrascale+ MPSoC, U1

Initial Delivery State

Storage device name	Content	Notes
User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT)	Empty	Not programmed
USB3 HUB Configuration EEPROM (Microchip 24LC128-I/ST)	Empty	Not programmed
Si5338A programmable PLL NVM OTP	Empty	Not programmed
Si5345A programmable PLL NVM OTP	Empty	Not programmed
eMMC Flash memory	Empty	Not programmed
2x QSPI Flash memory	Empty	Not programmed

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<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. -->

Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:

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	FMC A
	FMC A

FMC A

FMC A Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J10 (FMC A)	I/O	12	6	Bank 44 HD	FMCAF_1V8	-
	I/O	56	28	SC CPLD U27 Bank 1	FMCAF_1V8	-
	I²C	2	-	I²C-Switch U37	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 128 GTH	-	4x MGT lanes
	Clock Input	-	1	Bank 128 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'

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Table 7: FMC A connector cooling fan

Anchor

	FMC F
	FMC F

FMC F

FMC F Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J21 (FMC F)	I/O	12	6	Bank 44 HD	FMCAF_1V8	-
		28	14	SC CPLD U27 Bank 1	FMCAF_1V8	-
		28	14	SC CPLD U27 Bank 3	FMCAF_1V8	-
	I²C	2	-	I²C-Switch U37	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	4 (2 x RX/TX)	Bank 129 GTH	-	2x MGT lanes
	Clock Input	-	1	Bank 129 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'

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Table 12: FMC F connector cooling fan

Anchor

	FMC B
	FMC B

FMC B

FMC B Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J4 (FMC B)	I/O	24	12	Bank 47 HD	FMCBC_1V8	-
		20	10	Bank 48 HD	FMCBC_1V8	-
		24	12	Bank 49 HD	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 0	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 130 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 48 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 130 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

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Table 17: FMC B connector cooling fan

Anchor

	FMC C
	FMC C

FMC C

FMC C Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J8 (FMC C)	I/O	20	10	Bank 50 HD	FMCBC_1V8	-
	I/O	48	24	Bank 67 HP	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 230 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 50 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 230 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'

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Table 22: FMC C connector cooling fan

Anchor

	FMC D
	FMC D

FMC D

FMC D Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J7 (FMC D)	I/O	20	10	Bank 65 HP	FMCDE_1V8	-
	I/O	48	24	Bank 66 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 229 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 65 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 229 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

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Table 27: FMC D connector cooling fan

Anchor

	FMC E
	FMC E

FMC E

FMC E Interfaces:

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J6 (FMC E)	I/O	24	12	Bank 65 HP	FMCDE_1V8	-
	I/O	44	22	Bank 64 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 228 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 64 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 228 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

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title	Figure 4: XMOD header J24 and J35

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Signal Assignment of XMOD header J24 and J35

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title	Figure 6: USB3 interface

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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

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title	Figure 7: SFP+ interface

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Connector	Interface	Signal Schematic Name	Connected to	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P B129_TX3_N B129_RX3_P B129_RX3_N	MGTHTXP3_129, G31 MGTHTXN3_129, G32 MGTHRXP3_129, F33 MGTHRXN3_129, F34	TX: Output RX: Input	Multi gigabit highspeed data lane
	I²C	SFP0_SDA SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output, low active	Full RX bandwidth
		SFP0_RS1		Output, low active	Reduced RX bandwidth
		SFP0_M-DEF0		Input, low active	Module present / not present
		SFP0_TX_FAULT		Input, high active	Fault / Normal Operation
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input, high active	Loss of receiver signal
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output, low active	SFP Enabled / Disabled
SFP+ J9B	MGT Lane	B129_TX2_P B129_TX2_N B129_RX2_P B129_RX2_N	MGTHTXP2_129, H29 MGTHTXN2_129, H30 MGTHRXP2_129, H33 MGTHRXN2_129, H34	TX: Output RX: Input	Multi gigabit highspeed data lane
	I²C	SFP1_SDA SFP1_SCL	8-channel I²C-switch U37	Bidir	2-wire Serial Interface
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output, low active	Full RX bandwidth
		SFP1_RS1		Output, low active	Reduced RX bandwidth
		SFP1_M-DEF0		Input, low active	Module present / not present
		SFP1_TX_FAULT		Input, high active	Fault / Normal Operation
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input, high active	Loss of receiver signal
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output. low active	SFP Enabled / Disabled

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anchor	Figure_8
title	Figure 8: SSD interface

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Connector	Interface	Signal Schematic Name	Connected to	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N	PS_MGTRTXP0_505, AB29 PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 PS_MGTRTXN0_505, AB34	Multi gigabit highspeed data lane TX: Output RX: Input
	Clock Input	SSD_RCLK_P SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	Reference clock signal
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	LED, Output, High active
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	PCIe sleep state, Input, Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	PCIe reset, Input, Low active
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	PCIe Link reactivation, Input, Low active
		SSD1_CLKRQ	connect to GND	PCIe Clock Request, Low active

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title	Figure 9: DisplayPort interface

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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

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title	Figure 10: DDR4 memory interface

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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

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title	Figure 12: SD Card interface

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The SD Card socket have following signal and pin assignment:

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title	Figure 14: PLL clock interface

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Connector

Signal Schematic Name

Connected to

Notes

Pin Header

J22

PLL_SCL

clock generator U17, pin 16

PS_1V8 VCCIO

PLL_SDA

clock generator U17, pin 18

SMA Coax

J25

CLK_PLL_IN

clock generator U17, pin 1

-

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Table 65: Module hardware revision history

Hardware revision number can be found on the PCB board together with the board model number separated by the dash.

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Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat
showVersions	false

Figure 1: fixed Zynq to FMC IO count to 148

2019-08-27

v.184

John Hartfiel

typo

2019-05-10

v.183

John Hartfiel

correction of J8 Pin count description

2018-07-23

v.182

Ali Naseri

Initial document

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all

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infoType	Modified users
type	Flat
showVersions	false

Table 66: Document change history

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Trenz Electronic Documentation

Versions Compared

Old Version 185

New Version Current

Key

Main Components

Initial Delivery State