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Table of Contents
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Overview
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<!-- Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0712 --> |
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JTAG access to the ... is provided through B2B XMOD connector ....
JTAG Signal | B2B Connector Pin |
|---|---|
| TCK | JMx-xx |
| TDI | JMx-xx |
| TDO | JMx-xx |
| TMS | JMx-xx |
Table 5: JTAG interface signals.
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Gigabit Ethernet Interface
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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | B2B Connector Pin | Default Configuration |
|---|---|---|---|---|
| PGOOD | Output | Power Good | J1-148 | Active high when all on-module power supplies are working properly. |
| JTAGEN | Input | JTAG Select | J2-131 | Low for normal operation. |
| .. | .. | .. | .. | .. |
Table x: System Controller CPLD I/O pins.
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USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).
| PHY Pin | Connected to | Notes |
|---|---|---|
| ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY |
| REFCLK | - | 52MHz from on board oscillator (U9) |
| REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) |
| RESETB | SC CPLD U17 | Low active USB PHY Reset (pulled-up to PS_1.8V). |
| DP, DM | 4-port USB3.0 Hub U4 | USB2.0 data lane |
| CPEN | - | External USB power switch active-high enable signal |
| VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic |
| ID | - | For an A-device connect to the ground. For a B-device, leave floating |
Table 17: USB PHY interface connections
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On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.
| PHY Pin | Connected to | Notes |
|---|---|---|
| MDC/MDIO | PS bank MIO76, MIO77 | - |
| PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
| PHY_LED2 / INTn: | SC CPLD U17, pin 85 | Active low interrupt line |
| PHY_CLK125M | SC CPLD U17, pin 70 | 125 MHz Ethernet PHY clock out |
| CONFIG | SC CPLD U17, pin 65 | Configuration of PHY address LSB and VDDO level |
| RESETn | SC CPLD U17, pin 62 | Active low reset line |
| RGMII | PS bank MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
| SGMII | - | Serial Gigabit Media Independent Interface |
| MDI | RJ45 GbE MagJack J7 | Media Dependent Interface |
Table 18: Ethernet PHY interface connections
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The I2C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) configured as master.
| MIO | Signal Schematic Name | Notes |
|---|---|---|
| 38 | I2C_SCL | 1.8V reference voltage |
| 39 | I2C_SDA | 1.8V reference voltage |
Table 19: MIO-pin assignment of the module's I2C interface
I2C addresses for on-board slave devices are listed in the table below:
| I²C Slave Devices connected to MPSoC I²C Interface | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
|---|---|---|---|
| 8-channel I²C switch U16 | - | 0x73 | I2C_SDA / I2C_SCL |
| 8-channel I²C switch U27 | - | 0x77 | I2C_SDA / I2C_SCL |
| SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL) | - | User programmable | I2C_SDA / I2C_SCL |
| I²C Slave Devices connected to 8-channel I²C Switch U16 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
| On-board Quad programmable PLL clock generator U35 Si5338 | 0 | 0x70 | MCLK_SDA / MCLK_SCL |
| 8-bit I²C IO Expander U44 | 1 | 0x26 | SFP_SDA / SFP_SCL |
| PCIe Connector J1 | 2 | module dependent | PCIE_SDA / PCIE_SCL |
| SFP+ Connector J14A | 3 | module dependent | SFP1_SDA / SFP1_SCL |
| SFP+ Connector J14B | 4 | module dependent | SFP2_SDA / SFP2_SCL |
| Configuration EEPROM U24 | 5 | 0x54 | MEM_SDA / MEM_SCL |
| Configuration EEPROM U36 | 5 | 0x52 | MEM_SDA / MEM_SCL |
| Configuration EEPROM U41 | 5 | 0x51 | MEM_SDA / MEM_SCL |
| Configuration EEPROM U22 | 5 | 0x50 | MEM_SDA / MEM_SCL |
| 8-bit I²C IO Expander U38 | 5 | 0x27 | MEM_SDA / MEM_SCL |
| FMC Connector J5 | 6 | module dependent | FMC_SDA / FMC_SCL |
| USB3.0 Hub configuration EEPROM U5 | 7 | 0x51 | USBH_SDA / USBH_SCL |
| USB3.0 Hub | 7 | 0x60 | USBH_SDA / USBH_SCL |
| I²C Slave Devices connected to 8-channel I²C Switch U27 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
| PMOD Connector P1 | 0 | module dependent | PMOD_SDA / PMOD_SCL |
| 24-bit Audio Codec U3 | 1 | 0x38 | A_I2C_SDA / A_I2C_SCL |
| FireFly Connector J15 | 2 | module dependent | FFA_SDA / FFA_SCL |
| FireFly Connector J22 | 3 | module dependent | FFB_SDA / FFB_SCL |
| On-module Quad programmable PLL clock generator Si5345 (TE0808) | 4 | 0x69 | PLL_SDA / PLL_SCL |
| SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL) | 5 | User programmable | SC_SDA / SC_SCL |
| 8-bit I²C IO Expander U34 | 6 | 0x24 | FF_E_SDA / FF_E_SCL |
| PMOD Connector P3 | 7 | module dependent | EXT_SDA / EXT_SCL |
Table 20: On-board peripherals' I2C-interfaces device slave addresses
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The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
| EEPROM Modell | Schematic Designator | Memory Density | Purpose |
|---|---|---|---|
| 24LC128-I/ST | U24 | 128 Kbit | user |
| 24AA025E48T-I/OT | U36 | 2 Kbit | user |
| 24AA025E48T-I/OT | U41 | 2 Kbit | user |
| 24AA025E48T-I/OT | U42 | 2 Kbit | user |
| 24LC128-I/ST | U5 | 128 Kbit | USB3.0 Hub U4 configuration memory |
Table 21: On-board configuration EEPROMs overview
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The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
| Clock Source | Schematic Name | Frequency | Clock Input Destination |
|---|---|---|---|
| SiTime SiT8008BI oscillator, U10 | USB0_RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U9, pin 26 |
| SiTime SiT8008BI oscillator, U13 | ETH_CLK | 25.000000 MHz | Gigabit Ethernet PHY U12, pin 34 |
| SiTime SiT8008BI oscillator, U7 | - | 25.000000 MHz | Quad PLL clock generator U35, pin 3 |
| DSC1123 oscillator, U23 | B505_CLK1 | 150.0000 MHz | PS GT Bank, dedicated for SATA interface |
DSC1123 oscillator, U6 optional, not equipped | B505_CLK0 | 100.0000 MHz | PS GT Bank, dedicated for USB interface |
Silicon Labs 570FBB000290DG, U45 optional, not equipped | B47_L5 (LVDS) | 250.MHz | PL Bank clock capable input pins |
| SiTime SiT8008BI oscillator, U25 | CLK_CPLD | 25.576000 MHz | System Controller CPLD U35, pin 128 |
Table 16: Reference clock signal oscillators
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Overview
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