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Figure x: General overview of the FMC connectors
| FMC | Interfaces |
|---|
| I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
|---|---|---|---|---|
| J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD |
| FMCAF_1V8 | - | ||||
| 46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | |
| I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface |
| JTAG | 4 | - | SC CPLD U27 Bank 2 | 3. |
| 3VSB | - | ||||
| MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4 MGT Lanes |
| Clock Input | - | 1 | Bank 128 GTH | - | Reference Clock Input to MGT Bank |
| Control Signals |
| 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_ |
C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
PG = Power Good |
J21 |
J4 |
J8 | ||||||
J7 | ||||||
J6 |
Table
| HTML |
|---|
<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. --> |
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