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Table x: FMC connectors interfaces overview

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MGT lanes should be listed separately, as they are more specific than just general I/Os.
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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection FMC connector pin and FPGA pins connection:

Table x: MGT lanes.

Below are listed MGT banks reference clock sources.

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Table x: MGT reference clock sources.

TODO: FMC fans table, FMC available VCC/VCCIO table

XMOD Interface

JTAG access to the ... is provided through XMOD connector .... 

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