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Figure x: General overview of the FMC connectors

Following table shows an overview of the interfaces tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors:connectors  A - F:

FMC A Connector

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J10

(FMC A)





I/O126Bank 44 HDFMCAF_1V8-
4628SC CPLD U27 Bank 1FMCAF_1V8-
I²C2-I²C-Switch U37-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 128 GTH-4x MGT lanes
Clock Input-1Bank 128 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 03.3VSB

'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT'

Table 3: FMC A connector interfaces


FMCMGT LaneBankTypeSignal NameFMC Connector PinFPGA Pin

J10

(FMC A)


0128GTH
  • B128_RX0_P
  • B128_RX0_N
  • B128_TX0_P
  • B128_TX0_N
  • J10-C6
  • J10-C7
  • J10-C2
  • J10-C3
  • MGTHRXP0_128, T33
  • MGTHRXN0_128, T34
  • MGTHTXP0_128, T29
  • MGTHTXN0_128, T30
1128GTH
  • B128_RX1_P
  • B128_RX1_N
  • B128_TX1_P
  • B128_TX1_N
  • J10-A2
  • J10-A3
  • J10-A22
  • J10-A23
  • MGTHRXP1_128, P33
  • MGTHRXN1_128, P34
  • MGTHTXP1_128, R31
  • MGTHTXN1_128, R32
2128GTH
  • B128_RX2_P
  • B128_RX2_N
  • B128_TX2_P
  • B128_TX2_N
  • J10-A6
  • J10-A7
  • J10-A26
  • J10-A27
  • MGTHRXP2_128, N31
  • MGTHRXN2_128, N32
  • MGTHTXP2_128, P29
  • MGTHTXN2_128, P30
3128GTH
  • B128_RX3_P
  • B128_RX3_N
  • B128_TX3_P
  • B128_TX3_N
  • J10-A10
  • J10-A11
  • J10-A30
  • J10-A31
  • MGTHRXP3_128, M33
  • MGTHRXN3_128, M34
  • MGTHTXP3_128, M29
  • MGTHTXN3_128, M30

Table 4: FMC A connector MGT lanes


FMCClock SignalBankFMC Connector PinFPGA PinNotes

J10

(FMC A)

  • B128_CLK0_P
  • B128_CLK0_N
128
  • J10-D4
  • J10-D5
  • MGTREFCLK0P_128, R27
  • MGTREFCLK0N_128, R28
Supplied by attached module

Table 5: FMC A connector clock signal input


FMCAvailable VCC/VCCIOFMC Connector PinSourceNotes

J10

(FMC A)

FMCA_3V3
  • J10-D36
  • J10-D38
  • J10-D40
  • J10-C39

DCDC U32,
max. cur.: 5A

Enable by SC CPLD U27,

Signal: 'EN_A_3V3'

3V3SB
  • J10-D32

DCDC U50,

max. cur.: 1A		not dedicated for FMC
connectors
12V_FMC_AF
  • J10-C35
  • J10-C37

DCDC U51,
max. cur.: 5A

-
FMCAF_1V8
  • J10-H40
  • J10-G39
  • J10-F40
  • J10-E39

DCDC U39,
max. cur.: 5A

-

Table 6: FMC A connector available VCC/VCCIO


FMCFan DesignatorEnable SignalNotes

J10

(FMC A)

M1

Enable by SC CPLD U27,

Signal: 'FAN_A_EN'

-

Table 7: FMC A connector cooling fan

FMC F Connector

J21
(FMC F)
SC 229 2x Reference clock inputs to PL bank 229 2FMCDFMCDFMCD22 64 HPFMCDE
FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
J10
(FMC A)		I/O126Bank 44 HDFMCAF_1V8-


4628SC CPLD U27 Bank 1FMCAF_1V8-

I²C2-I²C-Switch U37-Muxed to MIO Bank 501 I²C Inteface

JTAG4-SC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotesI/O126Bank 44 HDFMCAF_1V8-
2814SC CPLD U27 Bank 1FMCAF_1V8-
6834SC CPLD U27 Bank 3FMCAF_1V8-
I²C2-I²C-Switch U37-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 129 GTH-4x MGT lanes
Clock Input-1Bank 129 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J4
(FMC B)

I/O2412Bank 47 HDFMCBC_1V8-
2010Bank 48 HDFMCBC_1V8-
2412Bank 49 HDFMCBC_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 03.3VSB-
MGT-8 (4 x RX/TX)Bank 130 GTH-4x MGT lanes
Clock Input-2Bank 48 HD-

2x Reference clock inputs to PL bank

-1Bank 130 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 03.3VSB

'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J8
(FMC C)

I/O2010Bank 50 HDFMCBC_1V8-
6834Bank 67 HPFMCBC_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 230 GTH-4x MGT lanes
Clock Input-2Bank 50 HD-

2x Reference clock inputs to PL bank

-1Bank 230 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J7
(FMC D)

I/O2010Bank 65 HPFMCDE_1V8-
4824Bank 66 HPFMCDE_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4- CPLD U27 Bank 23.3VSB-

MGT-8 (4 x RX/TX)Bank 128 GTH-4x MGT lanes

Clock Input-2Bank 65 HP--1Bank 128 GTH-1x Reference clock input to MGT bank

Control Signals3-SC CPLD U27 Bank 03.3VSB

'

FMCA_PG_C2M', '

FMCA_PG_M2C', '

FMCA_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
J21J6
(FMC EF)

I/O2412Bank 65 HP126Bank 44 HDFMCAF_1V8-
2814SC CPLD U27 Bank 1FMCAFFMCDE_1V8-44
6834SC CPLD U27 Bank 3FMCAF_1V8-
I²C2-I²C-Switch U13U37-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 228 129 GTH-4x MGT lanes
Clock Input-2Bank 64 HP-

2x Reference clock inputs to PL bank

-1Bank 228 129 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCEFMCF_PG_C2M', 'FMCEFMCF_PG_M2C', 'FMCEFMCF_PRSNT'

Table x: FMC connectors interfaces overview

HTML
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
  -->

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin and FPGA pins:

...

  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N

...

  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9

...

  • MGTHRXP0_225, Y2
  • MGTHRXN0_225, Y1
  • MGTHTXP0_225, AA4
  • MGTHTXN0_225, AA3

...

  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N

...

  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15

...

  • MGTHRXP1_225, V2
  • MGTHRXN1_225, V1
  • MGTHTXP1_225, W4
  • MGTHTXN1_225, W3

...

  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N

...

  • JM1-12
  • JM1-10
  • JM1-6
  • JM1-4

...

  • MGTHRXP0_224, AH2
  • MGTHRXN0_224, AH1
  • MGTHTXP0_224, AG4
  • MGTHTXN0_224, AG3

...

  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N

...

  • JM1-24
  • JM1-22
  • JM1-18
  • JM1-16

...

  • MGTHRXP1_224, AF2
  • MGTHRXN1_224, AF1
  • MGTHTXP1_224, AF6
  • MGTHTXN1_224, AF5
FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J4
(FMC B)

I/O2412Bank 47 HDFMCBC_1V8-
2010Bank 48 HDFMCBC_1V8-
2412Bank 49 HDFMCBC_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 03.3VSB-
MGT-8 (4 x RX/TX)Bank 130 GTH-4x MGT lanes
Clock Input-2Bank 48 HD-

2x Reference clock inputs to PL bank

-1Bank 130 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 03.3VSB

'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J8
(FMC C)

I/O2010Bank 50 HDFMCBC_1V8-
6834Bank 67 HPFMCBC_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 230 GTH-4x MGT lanes
Clock Input-2Bank 50 HD-

2x Reference clock inputs to PL bank

-1Bank 230 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J7
(FMC D)

I/O2010Bank 65 HPFMCDE_1V8-
4824Bank 66 HPFMCDE_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 229 GTH-4x MGT lanes
Clock Input-2Bank 65 HP-

2x Reference clock inputs to PL bank

-1Bank 229 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

FMC
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes

J6
(FMC E)








I/O2412Bank 65 HPFMCDE_1V8-
4422Bank 64 HPFMCDE_1V8-
I²C2-I²C-Switch U13-Muxed to MIO Bank 501 I²C Inteface
JTAG4-SC CPLD U27 Bank 23.3VSB-
MGT-8 (4 x RX/TX)Bank 228 GTH-4x MGT lanes
Clock Input-2Bank 64 HP-

2x Reference clock inputs to PL bank

-1Bank 228 GTH-1x Reference clock input to MGT bank
Control Signals3-SC CPLD U27 Bank 23.3VSB

'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

Table x: FMC connectors interfaces overview


HTML
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
  -->

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin and FPGA pins:

...











































Table x: MGT lanes


Below are listed MGT banks reference clock sources.

...