Page History
...
draw.io Diagram | ||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Figure x: General overview of the FMC connectors
Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:
FMC A Interfaces
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
Table 3: FMC A connector interfaces
FMC A MGT Lanes
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J10 (FMC A) | 0 | 128 | GTH |
|
|
|
1 | 128 | GTH |
|
|
| |
2 | 128 | GTH |
|
|
| |
3 | 128 | GTH |
|
|
|
Table 4: FMC A connector MGT lanes
FMC A Clock Signals
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J10 (FMC A) |
| 128 |
|
| Supplied by attached module |
Table 5: FMC A connector clock signal input
FMC A VCC/
...
VCCIO
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J10 (FMC A) | FMCA_3V3 |
| DCDC U32, | Enable by SC CPLD U27, Signal: 'EN_A_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | Enable by SC CPLD U27, Signal: 'EN_AF_1V8' |
Table 6: FMC A connector available VCC/VCCIO
FMC A Cooling Fan
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J10 (FMC A) | M1 | Enable by SC CPLD U27, Signal: 'FAN_A_EN' | - |
Table 7: FMC A connector cooling fan
FMC F Interfaces
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J21 (FMC F) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
28 | 14 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
68 | 34 | SC CPLD U27 Bank 3 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 4 (4 2 x RX/TX) | Bank 129 GTH | - | 4x 2x MGT lanes | |
Clock Input | - | 1 | Bank 129 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT' |
Table 8: FMC F connector interface
FMC F MGT Lanes
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J21 (FMC F) | 0 | 128129 | GTH |
|
|
|
1 | 128129 | GTH |
|
|
| |
2 | 128 | GTH |
|
|
| |
3 | 128 | GTH |
|
|
|
Table 9: FMC F connector MGT lanes
FMC F Clock Signals
...
J21
(FMC F)
...
- B128_CLK0_P
- B128_CLK0_N
...
- J10-D4
- J10-D5
...
- MGTREFCLK0P_128, R27
- MGTREFCLK0N_128, R28
...
|
Table 9: FMC F connector MGT lanes
FMC F Clock Signals
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J21 (FMC F) |
| 129 |
|
| Supplied by attached module |
Table 10: FMC F connector clock signal input
FMC F VCC/VCCIO
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J21 (FMC F) | FMCF_3V3 |
| DCDC U42, | Enable by SC CPLD U27, Signal: 'EN_A_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | Enable by SC CPLD U27, Signal: 'EN_AF_1V8' |
Table 11: FMC F connector available VCC/VCCIO
FMC F Cooling Fan
FMC | Fan Designator | Enable Signal |
---|
Table 10: FMC F connector clock signal input
FMC F VCC/VCCIOs
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes | ||||
---|---|---|---|---|---|---|---|---|
J21 (FMC F) | FMCA_3V3 |
| DCDC U32, | M6 | Enable by SC CPLD U27, Signal: 'ENFAN_AF_3V3EN' 3V3SB | J10-D32 | DCDC U50, max. cur.: 1A | not dedicated for FMC connectors |
12V_FMC_AF |
| DCDC U51, | - | |||||
FMCAF_1V8 |
| DCDC U39, | - |
Table 11: FMC F connector available VCC/VCCIO
FMC F Cooling Fan
...
J21
(FMC F)
...
Enable by SC CPLD U27,
Signal: 'FAN_F_EN'
...
Table 12: FMC F connector cooling fan
FMC B Interfaces
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J4 | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - |
20 | 10 | Bank 48 HD | FMCBC_1V8 | - | ||
24 | 12 | Bank 49 HD | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 0 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 130 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 48 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 130 |
Table 12: FMC F connector cooling fan
(FMC F)
GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank |
0 | 3.3VSB | ' |
FMCB_PG_C2M', ' |
FMCB_PG_M2C', ' |
FMCB_PRSNT' |
Table 13: FMC B connector interfaces
FMC B MGT Lanes
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|
J4 (FMC B) |
3 |
130 |
GTH |
|
|
| ||
2 | 130 | GTH |
|
|
|
1 | 130 | GTH |
|
|
|
0 | 130 | GTH |
|
|
|
Table 14: FMC B connector MGT lanes
FMC B Clock Signals
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J4 (FMC B) |
| 130 |
|
| Supplied by attached module |
| 48 HD |
|
| Supplied by attached module | |
| 48 HD |
|
| Supplied by attached module |
Table 15: FMC B connector clock signal input
FMC B VCC/VCCIO
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J4 (FMC B) | FMCB_3V3 |
| DCDC U33, | Enable by SC CPLD U27, Signal: 'EN_B_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCBC_1V8 |
| DCDC U40, | Enable by SC CPLD U27, Signal: 'EN_BC_1V8' |
Table 16: FMC B connector available VCC/VCCIO
FMC B Cooling Fan
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J4 (FMC B) | M2 | Enable by SC CPLD U27, Signal: 'FAN_B_EN' | - |
Table 17: FMC B connector cooling fan
FMC C Interfaces
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J8 | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - |
68 | 34 | Bank 67 HP | FMCBC |
2x Reference clock inputs to PL bank
'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'
J8
(FMC C)
2x Reference clock inputs to PL bank
'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'
J7
(FMC D)
2x Reference clock inputs to PL bank
'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'
J6
(FMC E)
_1V8 | - | ||||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - |
MGT | - | 8 (4 x RX/TX) | Bank |
230 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank |
50 HD | - | 2x Reference clock inputs to PL bank |
- | 1 | Bank |
230 GTH | - | 1x Reference clock input to MGT bank | |||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | ' |
FMCC_PG_C2M', ' |
FMCC_PG_M2C', ' |
FMCC_PRSNT' |
Table x: FMC connectors interfaces overview
HTML |
---|
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
--> |
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, FMC connector pin and FPGA pins:
Table x: MGT lanes
Below are listed MGT banks reference clock sources.
...
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT' |
Table 18: FMC C connector interfaces
FMC C MGT Lanes
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J8 (FMC C) | 3 | 230 | GTH |
|
|
|
2 | 230 | GTH |
|
|
| |
1 | 230 | GTH |
|
|
| |
0 | 230 | GTH |
|
|
|
Table 19: FMC C connector MGT lanes
FMC C Clock Signals
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J8 (FMC C) |
| 230 |
|
| Supplied by attached module |
| 50 HD |
|
| Supplied by attached module | |
| 50 HD |
|
| Supplied by attached module |
Table 20: FMC C connector clock signal input
FMC C VCC/VCCIO
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J8 (FMC C) | FMCC_3V3 |
| DCDC U34, | Enable by SC CPLD U27, Signal: 'EN_C_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCBC_1V8 |
| DCDC U40, | Enable by SC CPLD U27, Signal: 'EN_BC_1V8' |
Table 21: FMC C connector available VCC/VCCIO
FMC C Cooling Fan
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J8 (FMC C) | M3 | Enable by SC CPLD U27, Signal: 'FAN_C_EN' | - |
Table 22: FMC C connector cooling fan
FMC D Interfaces
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J7 | I/O | 20 | 10 | Bank 65 HP | FMCDE_1V8 | - |
48 | 24 | Bank 66 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 229 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 65 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 229 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT' |
Table 23: FMC D connector interfaces
FMC D MGT Lanes
FMC | MGT Lane | Bank | Type | Signal Name | FMC Donnector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J7 (FMC D) | 3 | 229 | GTH |
|
|
|
2 | 229 | GTH |
|
|
| |
1 | 229 | GTH |
|
|
| |
0 | 229 | GTH |
|
|
|
Table 24: FMC D connector MGT lanes
FMC D Clock Signals
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J7 (FMC D) |
| 229 |
|
| Supplied by attached module |
| 65 HP |
|
| Supplied by attached module | |
| 65 HP |
|
| Supplied by attached module |
Table 25: FMC D connector clock signal input
FMC D VCC/VCCIO
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J7 (FMC D) | FMCD_3V3 |
| DCDC U35, | Enable by SC CPLD U27, Signal: 'EN_D_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCDE_1V8 |
| DCDC U41, | Enable by SC CPLD U27, Signal: 'EN_DE_1V8' |
Table 26: FMC D connector available VCC/VCCIO
FMC D Cooling Fan
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J7 (FMC D) | M4 | Enable by SC CPLD U27, Signal: 'FAN_D_EN' | - |
Table 27: FMC D connector cooling fan
FMC E Interfaces
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J6 | I/O | 24 | 12 | Bank 65 HP | FMCDE_1V8 | - |
44 | 22 | Bank 64 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 228 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 228 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT' |
Table 28: FMC E connector interfaces
FMC E MGT Lanes
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J6 (FMC E) | 3 | 228 | GTH |
|
|
|
2 | 228 | GTH |
|
|
| |
1 | 228 | GTH |
|
|
| |
0 | 228 | GTH |
|
|
|
Table 29: FMC E connector MGT lanes
FMC E Clock Signals
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J6 (FMC E) |
| 228 |
|
| Supplied by attached module |
| 64 HP |
|
| Supplied by attached module | |
| 64 HP |
|
| Supplied by attached module |
Table 30: FMC E connector clock signal input
FMC E VCC/VCCIO
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J6 (FMC E) | FMCE_3V3 |
| DCDC U36, | Enable by SC CPLD U27, Signal: 'EN_E_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCDE_1V8 |
| DCDC U41, | Enable by SC CPLD U27, Signal: 'EN_DE_1V8' |
Table 31: FMC E connector available VCC/VCCIO
FMC E Cooling Fan
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J6 (FMC E) | M5 | Enable by SC CPLD U27, Signal: 'FAN_E_EN' | - |
Table 32: FMC E connector cooling fan
HTML |
---|
<!--
MGT lanes should be listed separately, as they are more specific than just general I/Os.
--> |
Table x: MGT reference clock sources
...
XMOD Interface
JTAG access to the ... is provided through XMOD connector ....
...