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Table 12: FMC F connector cooling fan

FMC B Interfaces

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J4 (FMC B)	I/O	24	12	Bank 47 HD	FMCBC_1V8	-
		20	10	Bank 48 HD	FMCBC_1V8	-
		24	12	Bank 49 HD	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 0	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 130 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 48 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 130 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

Table 13: FMC B connector interfaces

FMC B MGT Lanes

FMC	MGT Lane	Bank	Type	Signal Name	FMC Connector Pin	FPGA Pin
J4 (FMC B)	3	130	GTH	B130_RX3_P B130_RX3_N B130_TX3_P B130_TX3_N	J4-C6 J4-C7 J4-C2 J4-C3	MGTHRXP3_130, B33 MGTHRXN3_130, B34 MGTHTXP3_130, A31 MGTHTXN3_130, A32
	2	130	GTH	B130_RX2_P B130_RX2_N B130_TX2_P B130_TX2_N	J4-A2 J4-A3 J4-A22 J4-A23	MGTHRXP2_130, C31 MGTHRXN2_130, C32 MGTHTXP2_130, B29 MGTHTXN2_130, B30
	1	130	GTH	B130_RX1_P B130_RX1_N B130_TX1_P B130_TX1_N	J4-A6 J4-A7 J4-A26 J4-A27	MGTHRXP1_130, D33 MGTHRXN1_130, D34 MGTHTXP1_130, D29 MGTHTXN1_130, D30
	0	130	GTH	B130_RX0_P B130_RX0_N B130_TX0_P B130_TX0_N	J4-A10 J4-A11 J4-A30 J4-A31	MGTHRXP0_130, E31 MGTHRXN0_130, E32 MGTHTXP0_130, F29 MGTHTXN0_130, F30

Table 14: FMC B connector MGT lanes

FMC B Clock Signals

FMC

Clock Signal

Bank

FMC Connector Pin

FPGA Pin

Notes

J4

(FMC B)

B130_CLK0_P
B130_CLK0_N

130

J4-D4
J4-D5

MGTREFCLK0P_130, G27
MGTREFCLK0N_130, G28

Supplied by attached module

B_CLK0_M2C_P
B_CLK0_M2C_N

48 HD

J4-H4
J4-H5

IO_L6P_HDGC_48, F17
IO_L6N_HDGC_48, F18

Supplied by attached module

B_CLK1_M2C_P
B_CLK1_M2C_N

48 HD

J4-G2
J4-G3

IO_L5P_HDGC_48, G18
IO_L5N_HDGC_48, G19

Supplied by attached module

Table 15: FMC B connector clock signal input

FMC B VCC/VCCIO

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J4 (FMC B)	FMCB_3V3	J4-D36 J4-D38 J4-D40 J4-C39	DCDC U33, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_B_3V3'
	3V3SB	J4-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J4-C35 J4-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCBC_1V8	J4-H40 J4-G39 J4-F40 J4-E39	DCDC U40, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_BC_1V8'

Table 16: FMC B connector available VCC/VCCIO

FMC B Cooling Fan

FMC

Fan Designator

Enable Signal

Notes

J4

(FMC B)

M2

Enable by SC CPLD U27,

Signal: 'FAN_B_EN'

-

Table 17: FMC B connector cooling fan

FMC C Interfaces

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J8 (FMC C)	I/O	20	10	Bank 50 HD	FMCBC_1V8	-
	I/O	68	34	Bank 67 HP	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 230 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 50 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 230 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

Table 18: FMC C connector interfaces

FMC C MGT Lanes

FMC	MGT Lane	Bank	Type	Signal Name	FMC Connector Pin	FPGA Pin
J8 (FMC C)	3	230	GTH	B230_RX3_P B230_RX3_N B230_TX3_P B230_TX3_N	J8-C6 J8-C7 J8-C2 J8-C3	MGTHRXP3_230, A4 MGTHRXN3_230, A3 MGTHTXP3_230, A8 MGTHTXN3_230, A7
	2	230	GTH	B230_RX2_P B230_RX2_N B230_TX2_P B230_TX2_N	J8-A2 J8-A3 J8-A22 J8-A23	MGTHRXP2_230, B2 MGTHRXN2_230, B1 MGTHTXP2_230, B6 MGTHTXN2_230, B5
	1	230	GTH	B230_RX1_P B230_RX1_N B230_TX1_P B230_TX1_N	J8-A6 J8-A7 J8-A26 J8-A27	MGTHRXP1_230, C4 MGTHRXN1_230, C3 MGTHTXP1_230, D6 MGTHTXN1_230, D5
	0	230	GTH	B230_RX0_P B230_RX0_N B230_TX0_P B230_TX0_N	J8-A10 J8-A11 J8-A30 J8-A31	MGTHRXP0_230, D2 MGTHRXN0_230, D1 MGTHTXP0_230, E4 MGTHTXN0_230, E3

Table 19: FMC C connector MGT lanes

FMC C Clock Signals

FMC

Clock Signal

Bank

FMC Connector Pin

FPGA Pin

Notes

J8

(FMC C)

B230_CLK0_P
B230_CLK0_N

230

J8-D4
J8-D5

MGTREFCLK0P_230, C8
MGTREFCLK0N_230, C7

Supplied by attached module

C_CLK0_M2C_P
C_CLK0_M2C_N

50 HD

J8-H4
J8-H5

IO_L7P_HDGC_50, J12
IO_L7N_HDGC_50, H12

Supplied by attached module

C_CLK1_M2C_P
C_CLK1_M2C_N

50 HD

J8-G2
J8-G3

IO_L8P_HDGC_50, H13
IO_L8N_HDGC_50, G13

Supplied by attached module

Table 20: FMC C connector clock signal input

FMC C VCC/VCCIO

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J8 (FMC C)	FMCC_3V3	J8-D36 J8-D38 J8-D40 J8-C39	DCDC U34, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_C_3V3'
	3V3SB	J8-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J8-C35 J8-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCBC_1V8	J8-H40 J8-G39 J8-F40 J8-E39	DCDC U40, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_BC_1V8'

Table 21: FMC C connector available VCC/VCCIO

FMC C Cooling Fan

FMC

Fan Designator

Enable Signal

Notes

J8

(FMC C)

M3

Enable by SC CPLD U27,

Signal: 'FAN_C_EN'

-

Table 22: FMC C connector cooling fan

FMC D Interfaces

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J7 (FMC D)	I/O	20	10	Bank 65 HP	FMCDE_1V8	-
	I/O	48	24	Bank 66 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 229 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 65 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 229 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

Table 23: FMC D connector interfaces

FMC D MGT Lanes

FMC	MGT Lane	Bank	Type	Signal Name	FMC Donnector Pin	FPGA Pin
J7 (FMC D)	3	229	GTH	B229_RX3_P B229_RX3_N B229_TX3_P B229_TX3_N	J7-C6 J7-C7 J7-C2 J7-C3	MGTHRXP3_229, F2 MGTHRXN3_229, F1 MGTHTXP3_229, F6 MGTHTXN3_229, F5
	2	229	GTH	B229_RX2_P B229_RX2_N B229_TX2_P B229_TX2_N	J7-A2 J7-A3 J7-A22 J7-A23	MGTHRXP2_229, H2 MGTHRXN2_229, H1 MGTHTXP2_229, G4 MGTHTXN2_229, G3
	1	229	GTH	B229_RX1_P B229_RX1_N B229_TX1_P B229_TX1_N	J7-A6 J7-A7 J7-A26 J7-A27	MGTHRXP1_229, J4 MGTHRXN1_229, J3 MGTHTXP1_229, H6 MGTHTXN1_229, H5
	0	229	GTH	B229_RX0_P B229_RX0_N B229_TX0_P B229_TX0_N	J7-A10 J7-A11 J7-A30 J7-A31	MGTHRXP0_229, K2 MGTHRXN0_229, K1 MGTHTXP0_229, K6 MGTHTXN0_229, K5

Table 24: FMC D connector MGT lanes

FMC D Clock Signals

FMC

Clock Signal

Bank

FMC Connector Pin

FPGA Pin

Notes

J7

(FMC D)

B229_CLK0_P
B229_CLK0_N

229

J7-D4
J7-D5

MGTREFCLK0P_229, G8
MGTREFCLK0N_229, G7

Supplied by attached module

D_CLK0_M2C_P
D_CLK0_M2C_N

65 HP

J7-H4
J7-H5

IO_L14P_T2L_N2_GC_65, AG5
IO_L14N_T2L_N3_GC_65, AG4

Supplied by attached module

D_CLK1_M2C_P
D_CLK1_M2C_N

65 HP

J7-G2
J7-G3

IO_L13P_T2L_N0_GC_QBC_65, AE5
IO_L13N_T2L_N1_GC_QBC_65, AF5

Supplied by attached module

Table 25: FMC D connector clock signal input

FMC D VCC/VCCIO

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J7 (FMC D)	FMCD_3V3	J7-D36 J7-D38 J7-D40 J7-C39	DCDC U35, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_D_3V3'
	3V3SB	J7-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J7-C35 J7-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCDE_1V8	J7-H40 J7-G39 J7-F40 J7-E39	DCDC U41, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_DE_1V8'

Table 26: FMC D connector available VCC/VCCIO

FMC D Cooling Fan

FMC

Fan Designator

Enable Signal

Notes

J7

(FMC D)

M4

Enable by SC CPLD U27,

Signal: 'FAN_D_EN'

-

Table 27: FMC D connector cooling fan

FMC E Interfaces

FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J6 (FMC E)	I/O	24	12	Bank 65 HP	FMCDE_1V8	-
	I/O	44	22	Bank 64 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 228 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 64 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 228 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

Table 28: FMC E connector interfaces

FMC E MGT Lanes

FMC	MGT Lane	Bank	Type	Signal Name	FMC Connector Pin	FPGA Pin
J6 (FMC E)	3	228	GTH	B228_RX3_P B228_RX3_N B228_TX3_P B228_TX3_N	J6-C6 J6-C7 J6-C2 J6-C3	MGTHRXP3_228, L4 MGTHRXN3_228, L3 MGTHTXP3_228, M6 MGTHTXN3_228, M5
	2	228	GTH	B228_RX2_P B228_RX2_N B228_TX2_P B228_TX2_N	J6-A2 J6-A3 J6-A22 J6-A23	MGTHRXP2_228, M2 MGTHRXN2_228, M1 MGTHTXP2_228, N4 MGTHTXN2_228, N3
	1	228	GTH	B228_RX1_P B228_RX1_N B228_TX1_P B228_TX1_N	J6-A6 J6-A7 J6-A26 J6-A27	MGTHRXP1_228, P2 MGTHRXN1_228, P1 MGTHTXP1_228, P6 MGTHTXN1_228, P5
	0	228	GTH	B228_RX0_P B228_RX0_N B228_TX0_P B228_TX0_N	J6-A10 J6-A11 J6-A30 J6-A31	MGTHRXP0_228, T2 MGTHRXN0_228, T1 MGTHTXP0_228, R4 MGTHTXN0_228, R3

Table 29: FMC E connector MGT lanes

FMC E Clock Signals

FMC

Clock Signal

Bank

FMC Connector Pin

FPGA Pin

Notes

J6

(FMC E)

B228_CLK0_P
B228_CLK0_N

228

J6-D4
J6-D5

MGTREFCLK0P_228, L8
MGTREFCLK0N_228, L7

Supplied by attached module

E_CLK0_M2C_P
E_CLK0_M2C_N

64 HP

J6-H4
J6-H5

IO_L12P_T1U_N10_GC_64, AL8
IO_L12N_T1U_N11_GC_64, AL7

Supplied by attached module

E_CLK1_M2C_P
E_CLK1_M2C_N

64 HP

J6-G2
J6-G3

IO_L11P_T1U_N8_GC_64, AK8
IO_L11N_T1U_N9_GC_64, AK7

Supplied by attached module

Table 30: FMC E connector clock signal input

FMC E VCC/VCCIO

FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J6 (FMC E)	FMCE_3V3	J6-D36 J6-D38 J6-D40 J6-C39	DCDC U36, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_E_3V3'
	3V3SB	J6-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J6-C35 J6-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCDE_1V8	J6-H40 J6-G39 J6-F40 J6-E39	DCDC U41, max. cur.: 5A	Enable by SC CPLD U27, Signal: 'EN_DE_1V8'

Table 31: FMC E connector available VCC/VCCIO

FMC E Cooling Fan

FMC

Fan Designator

Enable Signal

Notes

J6

(FMC E)

M5

Enable by SC CPLD U27,

Signal: 'FAN_E_EN'

-

Table 32: FMC E connector cooling fan

...

Trenz Electronic Documentation

Versions Compared

Old Version 53

New Version 54

Key

FMC B Interfaces

FMC B MGT Lanes

FMC B Clock Signals

FMC B VCC/VCCIO

FMC B Cooling Fan

FMC C Interfaces

FMC C MGT Lanes

FMC C Clock Signals

FMC C VCC/VCCIO

FMC C Cooling Fan

FMC D Interfaces

FMC D MGT Lanes

FMC D Clock Signals

FMC D VCC/VCCIO

FMC D Cooling Fan

FMC E Interfaces

FMC E MGT Lanes

FMC E Clock Signals

FMC E VCC/VCCIO

FMC E Cooling Fan