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Table 32: FMC E connector cooling fan
XMOD JTAG Interface
JTAG access to the ... Zynq MPSoC and SC CPLD is provided through XMOD connector ....
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JTAG Signal
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B2B Connector Pin
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header J24 and J35.
draw.io Diagram border true viewerToolbar true fitWindow false diagramName XMOD Header simpleViewer false width diagramWidth 462 revision 5
Figure X: XMOD header J24 and J35
Signal Assignment of XMOD header J24 and J35
| Connector | Interface | Signal Schematic Name | XMOD Header Pin | Connected to | VCCIO | VCC |
|---|---|---|---|---|---|---|
XMOD Header J24 | JTAG | F_TCK | J24-4 | Bank 503 PS Config, Pin R25 | PS_1V8 | 3V3SB |
| F_TDI | J24-10 | Bank 503 PS Config, Pin U25 | ||||
| F_TDO | J24-8 | Bank 503 PS Config, Pin T25 | ||||
| F_TMS | J24-12 | Bank 503 PS Config, Pin R24 | ||||
GPIO/ | XMOD2_A | J24-3 | SC CPLD Bank 5, Pin K7 | |||
| XMOD2_B | J24-7 | SC CPLD Bank 5, Pin K6 | ||||
| XMOD2_E | J24-9 | SC CPLD Bank 5, Pin H7 | ||||
| XMOD2_G | J24-11 | SC CPLD Bank 5, Pin H6 | ||||
XMOD Header J35 | JTAG | C_TCK | J35-4 | SC CPLD Bank 0, Pin A8 | 3V3SB | |
| C_TDI | J35-10 | SC CPLD Bank 0, Pin C7 | ||||
| C_TDO | J35-8 | SC CPLD Bank 0, Pin A6 | ||||
| C_TMS | J35-12 | SC CPLD Bank 0, Pin C9 | ||||
GPIO/ | XMOD1_A | J35-3 | SC CPLD Bank 0, Pin B19 | |||
| XMOD1_B | J35-9 | SC CPLD Bank 0, Pin A17 | ||||
| XMOD1_E | J35-7 | SC CPLD Bank 0, Pin C17 | ||||
| XMOD1_G | J35-11 | SC CPLD Bank 0, Pin A18 |
Table 33: XMOD interface signals
The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 board.
XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.
XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
| XMOD DIP-switches | Position |
|---|---|
| Switch 1 | ON |
| Switch 2 | OFF |
| Switch 3 | OFF |
| Switch 4 | OFF |
Table 34: XMOD adapter board DIP-switch positions for voltage configuration
| Note |
|---|
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
Gigabit Ethernet Interface
On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.
| PHY Pin | Connected to | Notes |
|---|---|---|
| MDC/MDIO | PS bank MIO76, MIO77 | - |
| PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
| PHY_LED2 / INTn: | SC CPLD U17, pin 85 | Active low interrupt line |
| PHY_CLK125M | SC CPLD U17, pin 70 | 125 MHz Ethernet PHY clock out |
| CONFIG | SC CPLD U17, pin 65 | Configuration of PHY address LSB and VDDO level |
| RESETn | SC CPLD U17, pin 62 | Active low reset line |
| RGMII | PS bank MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
| SGMII | - | Serial Gigabit Media Independent Interface |
| MDI | RJ45 GbE MagJack J7 | Media Dependent Interface |
Table 18: Ethernet PHY interface connections
Table 5: JTAG interface signals.
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USB3 Interface
SFP+ Interface
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