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Storage device name | Content | Notes |
|---|---|---|
| User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT) | Empty | Not programmed |
| USB3.0 HUB Configuration EEPROM (Microchip 24LC128-I/ST) | Empty | Not programmed |
| Si5338A programmable PLL NVM OTP | ||
| Si5345A programmable PLL NVM OTP |
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Figure x: General overview of the FMC connectors
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When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
| XMOD DIP-switches | Position |
|---|---|
| Switch 1 | ON |
| Switch 2 | OFF |
| Switch 3 | OFF |
| Switch 4 | OFF |
Table 34: XMOD adapter board DIP-switch positions for voltage configuration
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On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.
draw.io Diagram border true viewerToolbar true fitWindow false diagramName Gigabit Ethernet Interface simpleViewer false width diagramWidth 502 revision 3
Figure X: Gigabit Ethernet Interface
| PHY Pin | Connected to | Notes |
|---|---|---|
| MDC/MDIO | PS bank 502 MIO76, MIO77 | - |
| PHY LED0.. |
| 2 | SC CPLD |
| Bank 4, pin |
| L5, L1, |
| K1 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
| PHY_ |
| CLK125M | SC CPLD |
| Bank 4, pin |
| K2 | 125 MHz Ethernet PHY clock out |
| CONFIG |
| pulled up to PS_1V8 | Configuration of PHY address LSB and VDDO level |
| RESETn | SC CPLD |
| Bank 4, pin |
| L6 | Active low reset line | |
| RGMII | PS bank 502 MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
| SGMII | - | Serial Gigabit Media Independent Interface |
| MDI | RJ45 GbE MagJack |
| J13 | Media Dependent Interface |
Table 1835: Ethernet PHY interface connections
USB3 Interface
On the TEB0911 board two USB3.0 Superspeed ports are available to the user, which are downward compatible to USB2.0 Highspeed.
draw.io Diagram border true viewerToolbar true fitWindow false diagramName USB3 Interface simpleViewer false width diagramWidth 530 revision 2
Figure X: USB3 Interface
SFP+ Interface
SSD Interface
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