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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

IC	Interface	Signal Schematic Names	Connected to	Note
USB3 Hub U4	USB3 Upstream MGT lane	B505_TX1_N, B505_TX1_P B505_RX1_N, B505_RX1_P	PS GTR bank 505 Pins: PS_MGTRTXP1_505, Y29, PS_MGTRTXN1_505, Y30 PS_MGTRRXP1_505, AA31, PS_MGTRTXN1_505, AA32	-
	USB2 Uptream data LVDS pair	USB0_D_P USB0_D_N	USB2 PHY U15 Pins: 18,19	-
	USB3 Downstream lane	USB3_RXDN1_D_P, USB3_RXDN1_D_N USB3_TXDN1_D_P, USB3_TXDN1_D_N USB3_RXDN2_D_P, USB3_RXDN2_D_N USB3_TXDN2_D_P, USB3_TXDN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13
	USB2 Downstream LVDS pair	USB2_DN1_D_P, USB2_DN1_D_N USB2_DN2_D_P, USB2_DN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13
	I²C	USBH_SDA, USBH_SCL	Configuration EEPROM U5, 8-channel I²C-switch U37	EEPROM U5 is configuration and parameter memory of USB3 hub U4.
	Control Lines	USBH_MODE0, USBH_MODE1, USBH_RST	SC CPLD, Bank 2 Pins: Y17, Y16, Y15	-
USB2 PHY U15	USB2 ULPI	USB0_STP, USB0_NXT, USB0_DIR, USB0_CLK, USB0_DATA0 ... USB0_DATA7	PS bank 502 Pins: MIO52 ... MIO63	-
	USB2 data LVDS pair	USB0_D_P USB0_D_N	USB3 Hub U4 Pins: 71,72	-
	Control Lines	USB0_RST	SC CPLD, Bank 4 Pins: M2	-

Table 36: USB3 interface signals ans interfaces

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Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:

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anchor	SFP+
title	Figure x: SFP+ Interface

draw.io Diagram

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6

Figure X: SFP+ Interface

Signal Schematic Name	Connector Type	FPGA Direction	Description	Logic
SFPx_TX_DISABLE	SFP+	Output	SFP Enabled / Disabled	Low active
SFPx_LOS	SFP+	Input	Loss of receiver signal	High active
SFPx_RS0	SFP+	Output	Full RX bandwidth	Low active
SFPx_RS1	SFP+	Output	Reduced RX bandwidth	Low active
SFPx_M-DEF0	SFP+	Input	Module present / not present	Low active
SFPx_TX_FAULT	SFP+	Input	Fault / Normal Operation	High active
SFPx_I²C	SFP+	BiDir	2-wire Serial Interface	-
FFx_MPRS	FireFly	Output	depending on connected module	-
FFx_MSEL	FireFly	Outpute	depending on connected module	-
FFx_INTL	FireFly	Input	Module interrupt line	-
FFx_RSTL	FireFly	Output	Module reset line	-
FFx_I²C	FireFly	BiDir	2-wire Serial Interface	-

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