Page History

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IC	Interface	Signal Schematic Names	Connected to	Note
USB3 Hub U4	USB3 Upstream MGT lane	B505_TX1_NP, B505_TX1_PN B505_RX1_NP, B505_RX1_PN	PS GTR bank 505 Pins: PS_MGTRTXP1_505, Y29, PS_MGTRTXN1_505, Y30 PS_MGTRRXP1_505, AA31, PS_MGTRTXN1_505, AA32	-
	USB2 Uptream data LVDS pair	USB0_D_P, USB0_D_N	USB2 PHY U15 Pins: 18,19	-
	USB3 Downstream lane	USB3_RXDN1_D_P, USB3_RXDN1_D_N USB3_TXDN1_D_P, USB3_TXDN1_D_N USB3_RXDN2_D_P, USB3_RXDN2_D_N USB3_TXDN2_D_P, USB3_TXDN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	USB2 Downstream LVDS pair	USB2_DN1_D_P, USB2_DN1_D_N USB2_DN2_D_P, USB2_DN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	I²C	USBH_SDA, USBH_SCL	Configuration EEPROM U5, 8-channel I²C-switch U37	EEPROM U5 is configuration and parameter memory of USB3 hub U4
	Control Lines	USBH_MODE0, USBH_MODE1, USBH_RST	SC CPLD U27, bank 2 Pins: Y17, Y16, Y15	-
USB2 PHY U15	USB2 ULPI	USB0_STP, USB0_NXT, USB0_DIR, USB0_CLK, USB0_DATA0 ... USB0_DATA7	PS bank 502 Pins: MIO52 ... MIO63	-
	USB2 data LVDS pair	USB0_D_P, USB0_D_N	USB3 Hub U4 Pins: 71,72	-
	Control Lines	USB0_RST	SC CPLD U27, bank 4 Pin: M2	-

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draw.io Diagram

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viewerToolbar	true

fitWindow	false
diagramName	SSD Interface
simpleViewer	false
width
links	auto
tbstyle	hidden
lbox	true
diagramWidth	542
revision	2

Figure X: SSD Interface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic

SFP+ J9A

Notes

M.2-NGFF

PCIe Socket

U2

MGT Lane

B129

B505_

TX3

TX0_P,

B129

B505_

TX3

TX0_N

B129

B505_

RX3

RX0_P,

B129

B505_

RX3

RX0_N

GTH

PS GTR bank

129

505

Pins:

MGTHTXP3

PS_MGTRTXP0_

129

505,

G31

AB29,

MGTHTXN3

PS_MGTRTXN0_

129

505,

G32

AB30

MGTHRXP3

PS_MGTRRXP0_

129

505,

F33

AB33,

MGTHRXN3

PS_MGTRTXN0_

129

505,

F34

AB34

BiDir

Multi gigabit highspeed
data lane

-

I²CSFP0_SDA,
SFP0_SCL8-channel I²C-switch U37BiDir2-wire Serial Interface

Clock Input	SSD_RCLK_P, SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	-	Reference clock signal	-	-
Control Lines

SFP0

SSD1_

RS0I²C 8-bit I/O Port-Expander U86OutputFull RX bandwidthLow active

LED	SC CPLD U27, bank 2, pin W7	Output	LED Output	High active	-
SSD_SLEEP	SC CPLD U27, bank 2, pin W7	Input	PCIe Sleep	Low active
SSD_PERSTN

SFP0_RS1OutputReduced RX bandwidthLow activeSFP0_M-DEF0InputModule present / not presentLow activeSFP0_TX_FAULTInputFault / Normal OperationHigh activeSFP0_LOS

SC CPLD U27, bank 2, pin

V8

W7

Input

Loss of receiver signalHigh activeSFP0_TX_DIS

	PCIe nRST	Low	-
SSD_WAKE	SC CPLD U27, bank 2, pin

Y7

W7

OutputSFP Enabled / Disabled

Input	PCIe Wake	Low active	-
SSD_CLKRQ	connect to GND	Input	PCIe Clock Request	High active	-

Low active

DisplayPort Interface

DDR4 Memory Socket

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Trenz Electronic Documentation

Versions Compared

Old Version 78

New Version 79

Key

DisplayPort Interface

DDR4 Memory Socket