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IC	Interface	Signal Schematic Names	Connected to	Note
USB3 Hub U4	USB3 Upstream MGT lane	B505_TX1_P, B505_TX1_N B505_RX1_P, B505_RX1_N	PS GTR bank 505 Pins: PS_MGTRTXP1_505, Y29, PS_MGTRTXN1_505, Y30 PS_MGTRRXP1_505, AA31, PS_MGTRTXN1_505, AA32	-
	USB2 Uptream data LVDS pair	USB0_D_P, USB0_D_N	USB2 PHY U15 Pins: 18,19	-
	USB3 Downstream lane	USB3_RXDN1_D_P, USB3_RXDN1_D_N USB3_TXDN1_D_P, USB3_TXDN1_D_N USB3_RXDN2_D_P, USB3_RXDN2_D_N USB3_TXDN2_D_P, USB3_TXDN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	USB2 Downstream LVDS pair	USB2_DN1_D_P, USB2_DN1_D_N USB2_DN2_D_P, USB2_DN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	I²C	USBH_SDA, USBH_SCL	Configuration EEPROM U5, 8-channel I²C-switch U37	EEPROM U5 is configuration and parameter memory of USB3 hub U4
	Control Lines	USBH_MODE0, USBH_MODE1, USBH_RST	SC CPLD U27, bank 2 Pins: Y17, Y16, Y15	-
USB2 PHY U15	USB2 ULPI	USB0_STP, USB0_NXT, USB0_DIR, USB0_CLK, USB0_DATA0 ... USB0_DATA7	PS bank 502 Pins: MIO52 ... MIO63	-
	USB2 data LVDS pair	USB0_D_P, USB0_D_N	USB3 Hub U4 Pins: 71,72	-
	Control Lines	USB0_RST	SC CPLD U27, bank 4 Pin: M2	-

Table 36: USB3 interface signals and interfaces

SFP+ Interface

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Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P, B129_TX3_N B129_RX3_P, B129_RX3_N	GTH bank 129 Pins: MGTHTXP3_129, G31, MGTHTXN3_129, G32 MGTHRXP3_129, F33, MGTHRXN3_129, F34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP0_SDA, SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP0_RS1		Output	Reduced RX bandwidth	Low active
		SFP0_M-DEF0		Input	Module present / not present	Low active
		SFP0_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input	Loss of receiver signal	High active	-
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output	SFP Enabled / Disabled	Low active	-
SFP+ J9B	MGT Lane	B129_TX2_P, B129_TX2_N B129_RX2_P, B129_RX2_N	GTH bank 129 Pins: MGTHTXP2_129, H29, MGTHTXN2_129, H30 MGTHRXP2_129, H33, MGTHRXN2_129, H34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP1_SDA, SFP1_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP1_RS1		Output	Reduced RX bandwidth	Low active
		SFP1_M-DEF0		Input	Module present / not present	Low active
		SFP1_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input	Loss of receiver signal	High active	-
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output	SFP Enabled / Disabled	Low active	-

Table 37: SFP+ interface signals and interfaces

SSD Interface

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Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P, B505_TX0_N B505_RX0_P, B505_RX0_N	PS GTR bank 505 Pins: PS_MGTRTXP0_505, AB29, PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33, PS_MGTRTXN0_505, AB34	BiDir	Multi gigabit highspeed data lane	-	-
	Clock Input	SSD_RCLK_P, SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	-	Reference clock signal	-	-
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin W7AA13	Output	LED Output	High active	-
		SSDSSD1_SLEEP	SC CPLD U27, bank 2, pin W7AA12	Input	PCIe Sleep	Low active
		SSDSSD1_PERSTN	SC CPLD U27, bank 2, pin W7AA11	Input	PCIe nRST	Low active	-
		SSDSSD1_WAKE	SC CPLD U27, bank 2, pin W7AB11	InputOutput	PCIe Wake	Low High active	-
		SSDSSD1_CLKRQ	connect to GND	InputBiDir	PCIe Clock Request	High Low active	-

Table 38: SSD signals and interfaces

DisplayPort Interface

DDR4 Memory Socket

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SFP+ Interface

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DisplayPort Interface

DDR4 Memory Socket