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Anchor FMC A FMC A
FMC A
FMC A Interfaces:
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draw.io Diagram border true viewerToolbar true fitWindow false diagramName SSD Interface simpleViewer false width links auto tbstyle hidden lbox true diagramWidth 542 revision 23
Figure X: SSD Interface
Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Logic | Notes |
---|---|---|---|---|---|---|---|
M.2-NGFF PCIe Socket U2 | MGT Lane | B505_TX0_P, B505_RX0_P, | PS GTR bank 505 Pins: PS_MGTRRXP0_505, AB33, | BiDir | Multi gigabit highspeed data lane | - | - |
Clock Input | SSD_RCLK_P, SSD_RCLK_N | Quad programmable PLL clock generator U12, CLK0 | - | Reference clock signal | - | - | |
Control Lines | SSD1_LED | SC CPLD U27, bank 2, pin AA13 | OutputBiDir | LED Output | High active | - | |
SSD1_SLEEP | SC CPLD U27, bank 2, pin AA12 | Input | PCIe Sleep | Low active | |||
SSD1_PERSTN | SC CPLD U27, bank 2, pin AA11 | Input | PCIe nRST | Low active | - | ||
SSD1_WAKE | SC CPLD U27, bank 2, pin AB11 | Output | PCIe Wake | High active | - | ||
SSD1_CLKRQ | connect to GND | BiDir | PCIe Clock Request | Low active | - |
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