Page History
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| IC | Interface | Signal Schematic Names | Connected to | Note |
|---|---|---|---|---|
| USB3 Hub U4 | USB3 Upstream MGT lane | B505_TX1_P, B505_RX1_P, | PS GTR bank 505 Pins: PS_MGTRRXP1_505, AA31, | - |
| USB2 Uptream data LVDS pair | USB0_D_P, USB0_D_N | USB2 PHY U15 Pins: 18,19 | - | |
| USB3 Downstream lane | USB3_RXDN1_D_P, USB3_TXDN1_D_P, USB3_RXDN2_D_P, USB3_TXDN2_D_P, | 2-port USB3 A / RJ-45 connector | - | |
| USB2 Downstream LVDS pair | USB2_DN1_D_P, USB2_DN2_D_P, | 2-port USB3 A / RJ-45 connector | - | |
| I²C | USBH_SDA, USBH_SCL | Configuration EEPROM U5, 8-channel I²C-switch U37 | EEPROM U5 is configuration and | |
| Control Lines | USBH_MODE0, USBH_MODE1, USBH_RST | SC CPLD U27, bank 2 Pins: Y17, Y16, Y15 | - | |
| USB2 PHY U15 | USB2 ULPI | USB0_STP, | PS bank 502 Pins: MIO52 ... MIO63 | - |
| USB2 data LVDS pair | USB0_D_P, | USB3 Hub U4 Pins: 71,72 | - | |
| Control Lines | USB0_RST | SC CPLD U27, bank 4 Pin: M2 | - |
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| Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Logic | Notes |
|---|---|---|---|---|---|---|---|
M.2-NGFF PCIe Socket U2 | MGT Lane | B505_TX0_P, B505_RX0_P, | PS GTR bank 505 Pins: PS_MGTRRXP0_505, AB33, | BiDir | Multi gigabit highspeed data lane | - | - |
| Clock Input | SSD_RCLK_P, SSD_RCLK_N | Quad programmable PLL clock generator U12, CLK0 | - | Reference clock signal | - | - | |
| Control Lines | SSD1_LED | SC CPLD U27, bank 2, pin AA13 | Output | LED Output | High active | - | |
| SSD1_SLEEP | SC CPLD U27, bank 2, pin AA12 | Input | PCIe Sleep | Low active | |||
| SSD1_PERSTN | SC CPLD U27, bank 2, pin AA11 | Input | PCIe nRST | Low active | - | ||
| SSD1_WAKE | SC CPLD U27, bank 2, pin AB11 | Output | PCIe Wake | High active | - | ||
| SSD1_CLKRQ | connect to GND | BiDir | PCIe Clock Request | Low active | - |
Table 38: SSD signals and interfaces
DisplayPort Interface
DDR4 Memory Socket
CAN Interface
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interfaces
DisplayPort Interface
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DDR4 Memory Socket
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CAN Interface
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SD Card Interface
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Describe SD Card interface shortly here if the module has one...
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Table x: SD Card interface signals and connections.
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4-Wire PWM FAN Connectors
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PLL Clock Interfaces
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| diagramWidth | 508 |
| revision | 1 |
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On-board Peripherals
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<!-- Components on the Module, like Flash, PLL, PHY... --> |
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| Warning |
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| To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
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Figure : Module power-on diagram.
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Overview
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