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FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J10 (FMC A)	FMCA_3V3	J10-D36 J10-D38 J10-D40 J10-C39	DCDC U32, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin Y18 Signal: 'EN_A_3V3'
	3V3SB	J10-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V_FMC_AF	J10-C35 J10-C37	DCDC U51, max. cur.: 5A	-
	FMCAF_1V8	J10-H40 J10-G39 J10-F40 J10-E39	DCDC U39, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin W19 Signal: 'EN_AF_1V8'

Table 6: FMC A connector available VCC/VCCIO

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FMC

Fan Designator

Enable Signal

Notes

J10

(FMC A)

M1

Enable by SC CPLD U27, bank 2, pin Y19
Signal: 'FAN_A_EN'

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Table 7: FMC A connector cooling fan

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FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J21 (FMC F)	FMCF_3V3	J21-D36 J21-D38 J21-D40 J21-C39	DCDC U42, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin Y10 Signal: 'EN_AF_3V3'
	3V3SB	J21-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V_FMC_AF	J21-C35 J21-C37	DCDC U51, max. cur.: 5A	-
	FMCAF_1V8	J21-H40 J21-G39 J21-F40 J21-E39	DCDC U39, max. cur.: 5A	Enable by SC CPLD U27, bank 2, pin W19 Signal: 'EN_AF_1V8'

Table 11: FMC F connector available VCC/VCCIO

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FMC

Fan Designator

Enable Signal

Notes

J21

(FMC F)

M6

Enable by SC CPLD U27, bank 2, pin W18
Signal: 'FAN_F_EN'

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Table 12: FMC F connector cooling fan

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FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J4 (FMC B)	FMCB_3V3	J4-D36 J4-D38 J4-D40 J4-C39	DCDC U33, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin G11 Signal: 'EN_B_3V3'
	3V3SB	J4-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J4-C35 J4-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCBC_1V8	J4-H40 J4-G39 J4-F40 J4-E39	DCDC U40, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin A3 Signal: 'EN_BC_1V8'

Table 16: FMC B connector available VCC/VCCIO

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FMC

Fan Designator

Enable Signal

Notes

J4

(FMC B)

M2

Enable by SC CPLD U27, bank 0, pin A2
Signal: 'FAN_B_EN'

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Table 17: FMC B connector cooling fan

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FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J8 (FMC C)	FMCC_3V3	J8-D36 J8-D38 J8-D40 J8-C39	DCDC U34, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin E11 Signal: 'EN_C_3V3'
	3V3SB	J8-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J8-C35 J8-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCBC_1V8	J8-H40 J8-G39 J8-F40 J8-E39	DCDC U40, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin A3 Signal: 'EN_BC_1V8'

Table 21: FMC C connector available VCC/VCCIO

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FMC

Fan Designator

Enable Signal

Notes

J8

(FMC C)

M3

Enable by SC CPLD U27, bank 0, pin B3
Signal: 'FAN_C_EN'

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Table 22: FMC C connector cooling fan

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FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J7 (FMC D)	FMCD_3V3	J7-D36 J7-D38 J7-D40 J7-C39	DCDC U35, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin F8 Signal: 'EN_D_3V3'
	3V3SB	J7-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J7-C35 J7-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCDE_1V8	J7-H40 J7-G39 J7-F40 J7-E39	DCDC U41, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin C5 Signal: 'EN_DE_1V8'

Table 26: FMC D connector available VCC/VCCIO

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FMC

Fan Designator

Enable Signal

Notes

J7

(FMC D)

M4

Enable by SC CPLD U27, bank 0, pin D7
Signal: 'FAN_D_EN'

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Table 27: FMC D connector cooling fan

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FMC	Available VCC/VCCIO	FMC Connector Pin	Source	Notes
J6 (FMC E)	FMCE_3V3	J6-D36 J6-D38 J6-D40 J6-C39	DCDC U36, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin E8 Signal: 'EN_E_3V3'
	3V3SB	J6-D32	DCDC U50, max. cur.: 1A	not dedicated for FMC connectors
	12V	J6-C35 J6-C37	DCDC U82, max. cur.: 8A	not dedicated for FMC connectors
	FMCDE_1V8	J6-H40 J6-G39 J6-F40 J6-E39	DCDC U41, max. cur.: 5A	Enable by SC CPLD U27, bank 0, pin C5 Signal: 'EN_DE_1V8'

Table 31: FMC E connector available VCC/VCCIO

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FMC

Fan Designator

Enable Signal

Notes

J6

(FMC E)

M5

Enable by SC CPLD U27, bank 0, pin D6
Signal: 'FAN_E_EN'

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Table 32: FMC E connector cooling fan

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draw.io Diagram

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Figure X: SSD Interface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P, B505_TX0_N B505_RX0_P, B505_RX0_N	PS GTR bank 505 Pins: PS_MGTRTXP0_505, AB29, PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33, PS_MGTRTXN0_505, AB34	BiDir	Multi gigabit highspeed data lane	-	-
	Clock Input	SSD_RCLK_P, SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	-	Reference clock signal	-	-
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	Output	LED Output	High active	-
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	Input	PCIe Sleepsleep state	Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	Input	PCIe nRSTreset input	Low active	-
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	OutputInput	PCIe WakeLink reactivation	High Low active	-
		SSD1_CLKRQ	connect to GND	BiDir	PCIe Clock Request	Low active	-

Table 38: SSD signals and interfaces

DisplayPort Interface

The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is feeded by two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary dfdsf

draw.io Diagram

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fitWindow	false
diagramName	DisplayPort Interface
simpleViewer	false
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tbstyle	hidden
lbox	true
diagramWidth	492
revision	45

Figure X: DisplayPort Interface

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Trenz Electronic Documentation

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DisplayPort Interface