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IC	Interface	Signal Schematic Names	Connected to	Note
USB3 Hub U4	USB3 Upstream MGT lane	B505_TX1_P , B505_TX1_N B505_RX1_P , B505_RX1_N	PS GTR bank 505 Pins: PS_MGTRTXP1_505, Y29 , PS_MGTRTXN1_505, Y30 PS_MGTRRXP1_505, AA31 , PS_MGTRTXN1_505, AA32	-
	USB2 Uptream data LVDS pair	USB0_D_P , USB0_D_N	USB2 PHY U15 Pins: 18,19	-
	USB3 Downstream lane	USB3_RXDN1_D_P , USB3_RXDN1_D_N USB3_TXDN1_D_P , USB3_TXDN1_D_N USB3_RXDN2_D_P , USB3_RXDN2_D_N USB3_TXDN2_D_P , USB3_TXDN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	USB2 Downstream LVDS pair	USB2_DN1_D_P , USB2_DN1_D_N USB2_DN2_D_P , USB2_DN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	I²C	USBH_SDA , USBH_SCL	Configuration EEPROM U5, 8-channel I²C-switch U37	EEPROM U5 is configuration and parameter memory of USB3 hub U4
	Control Lines	USBH_MODE0, USBH_MODE1 , USBH_RST	SC CPLD U27, bank 2 Pins: Y17, Y16, Y15	-
USB2 PHY U15	USB2 ULPI	USB0_STP , USB0_NXT , USB0_DIR , USB0_CLK , USB0_DATA0 ... USB0_DATA7	PS bank 502 Pins: MIO52 ... MIO63	-
	USB2 data LVDS pair	USB0_D_P , USB0_D_N	USB3 Hub U4 Pins: 71,72	-
	Control Lines	USB0_RST	SC CPLD U27, bank 4 Pin: M2	-

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Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P , B129_TX3_N B129_RX3_P , B129_RX3_N	GTH bank 129 Pins: MGTHTXP3_129, G31 , MGTHTXN3_129, G32 MGTHRXP3_129, F33 , MGTHRXN3_129, F34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP0_SDA , SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP0_RS1		Output	Reduced RX bandwidth	Low active
		SFP0_M-DEF0		Input	Module present / not present	Low active
		SFP0_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input	Loss of receiver signal	High active	-
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output	SFP Enabled / Disabled	Low active	-
SFP+ J9B	MGT Lane	B129_TX2_P , B129_TX2_N B129_RX2_P , B129_RX2_N	GTH bank 129 Pins: MGTHTXP2_129, H29 , MGTHTXN2_129, H30 MGTHRXP2_129, H33 , MGTHRXN2_129, H34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP1_SDA , SFP1_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP1_RS1		Output	Reduced RX bandwidth	Low active
		SFP1_M-DEF0		Input	Module present / not present	Low active
		SFP1_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input	Loss of receiver signal	High active	-
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output	SFP Enabled / Disabled	Low active	-

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Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P , B505_TX0_N B505_RX0_P , B505_RX0_N	PS GTR bank 505 Pins: PS_MGTRTXP0_505, AB29 , PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 , PS_MGTRTXN0_505, AB34	BiDir	Multi gigabit highspeed data lane	-	-
	Clock Input	SSD_RCLK_P , SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	-	Reference clock signal	-	-
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	Output	LED Output	High active	-
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	Input	PCIe sleep state	Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	Input	PCIe reset input	Low active	-
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	Input	PCIe Link reactivation	Low active	-
		SSD1_CLKRQ	connect to GND	BiDir	PCIe Clock Request	Low active	-

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The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is feeded by two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary dfdsftransmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.

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Figure X: DisplayPort Interface

DDR4 Memory Socket

Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Notes
DisplayPort Connector J12	MGT Lane	B505_TX2_P B505_TX2_N B505_TX3_P B505_TX3_N	PS GTR bank 505 Pins: PS_MGTRTXP2_505, W31 PS_MGTRTXN2_505, W32 PS_MGTRTXP3_505, V29 PS_MGTRTXN3_505, V30	Output	Multi gigabit highspeed data lane (only transmit pairs)	-
	Auxiliary Line	DP_TX_AUX_P DP_TX_AUX_N	LVDS Line Driver/Receiver, U30	-	Convert signal from single ended to LVDS Single ended signals: 'DP_AUX_TX', 'DP_AUX_RX', SC CPLD U27, bank 2, pins AA14, AB12	-
	Control Lines	DP_TX_HPD	SC CPLD U27, bank 2, pin AA15	Input	DisplayPort Hot Plug Detect	-
	Control Lines	DP_EN	LDO U29	-	3.3V Supply Voltage for DisplayPort	-

Table 39: DisplayPort signals and interfaces

DDR4 Memory Socket

On the TEB0911 board there is a DDR4 memory interface with a 64-bit databus width available for SO-DIMM modules.

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Figure X: DDR4 memory interface

Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface

Connector	DDR4 SDRAM I/O Signal	Signal Schematic Name	Description	Connected to	Notes
DDR4 SO-DIMM Socket U13	Address inputs	DDR4-A0 ... DDR4-A16	-	PS DDR Bank 504	-
	Bank address inputs	DDR4-BA0 / DDR4-BA1	-		-
	Bank group inputs	DDR4-BG0 / DDR4-BG1	-		-
	Differential clocks	DDR4-CLK0_P DDR4-CLK0_N DDR4-CLK1_P DDR4-CLK1_N	2 x DDR4 clock		-
	Data input/output	DQ0 ... DQ63	-		-
	Check bit input/output	CB0 ... CB7	-		-
	Data strobe (differential)	DDR4-DQS0_P DDR4-DQS0_N ... DDR4-DQS8_P DDR4-DQS8_N	-		-
	Data mask and data bus inversion	DDR4-DM0 ... DDR4-DM8	-		-
	Serial address inputs	DDR4-SA0 ... DDR4-SA2	address range configuration on I²C bus		-
	Control Signals	DDR4-CS_N0 / DDR4-CS_N1	chip selest signal		-
		DDR4-ODT0 / DDR4-ODT1	On-die termination enable		-
		DDR4-RESET	nRESET		-
		DDR4-PAR	Command and address parity input		-
		DDR4-CKE0 / DDR4-CKE1	Clock enable		-
		DDR4-ALERT	CRC error flag		-
		DDR4-ACT	Activation command input		-
		DDR4-EVENT	Temperature event		-
	I²C	DDR4-SCL DDR4-SDA	-	8-channel I²C switch U37	-

Table 40: DDR4 64-bit memory interface signals and pins

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module. draw.io DiagrambordertrueviewerToolbartruefitWindowfalsediagramNameDDR4 Memory SocketsimpleViewerfalsewidthlinksautotbstylehiddenlboxtruediagramWidth584revision12Figure X: DDR4 memory Interface

CAN Interface

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draw.io Diagram

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Figure X: SD Card Interface

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Trenz Electronic Documentation

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DDR4 Memory Socket

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CAN Interface