Page History
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| Connector | DDR4 SDRAM I/O Signal | Signal Schematic Name | Description | Connected to | Notes |
|---|---|---|---|---|---|
DDR4 SO-DIMM Socket U13 | Address inputs | DDR4-A0 ... DDR4-A16 | - | PS DDR Bank 504 | - |
| Bank address inputs | DDR4-BA0 / DDR4-BA1 | - | - | ||
| Bank group inputs | DDR4-BG0 / DDR4-BG1 | - | - | ||
| Differential clocks |
| 2 x 2x DDR4 clock | - | ||
| Data input/output | DQ0 ... DQ63 | - | - | ||
| Check bit input/output | CB0 ... CB7 | - | - | ||
| Data strobe (differential) |
| 9x differential data lines | - | ||
| Data mask and data bus inversion | DDR4-DM0 ... DDR4-DM8 | - | - | ||
| Serial address inputs | DDR4-SA0 ... DDR4-SA2 | address range configuration | - | ||
| Control Signals | DDR4-CS_N0 / DDR4-CS_N1 | chip selest signal | - | ||
| DDR4-ODT0 / DDR4-ODT1 | On-die termination enable | - | |||
| DDR4-RESET | nRESET | - | |||
| DDR4-PAR | Command and address parity input | - | |||
| DDR4-CKE0 / DDR4-CKE1 | Clock enable | - | |||
| DDR4-ALERT | CRC error flag | - | |||
| DDR4-ACT | Activation command input | - | |||
| DDR4-EVENT | Temperature event | - | |||
| I²C |
| - | 8-channel I²C switch U37 | - |
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