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Figure X: XMOD header J24 and J35
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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:
| Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Notes |
|---|---|---|---|---|---|---|
DisplayPort Connector J12 | MGT Lane |
| PS GTR bank 505 Pins:
| Output | Multi gigabit highspeed data lane (only transmit pairs) | - |
| Auxiliary Line |
| LVDS Line Driver/Receiver, U30 | - | Convert signal from single ended to LVDS Single ended signals: 'DP_AUX_TX', 'DP_AUX_RX', | - | |
| Control Lines | DP_TX_HPD | SC CPLD U27, bank 2, pin AA15 | Input | DisplayPort Hot Plug Detect | - | |
| DP_EN | LDO U29 | - | 3.3V Supply Voltage for DisplayPort | - |
Table 39: DisplayPort signals and interfaces
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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface
| Connector | DDR4 SDRAM I/O Signal | Signal Schematic Name | Description | Connected to | Notes |
|---|---|---|---|---|---|
DDR4 SO-DIMM Socket U13 | Address inputs | DDR4-A0 ... DDR4-A16 | - | PS DDR Bank 504 | - |
| Bank address inputs | DDR4-BA0 / DDR4-BA1 | - | - | ||
| Bank group inputs | DDR4-BG0 / DDR4-BG1 | - | - | ||
| Differential clocks |
|
| 2 x DDR4 clock | - | ||
| Data input/output | DQ0 ... DQ63 | - | - |
| Check bit input/output | CB0 ... CB7 | - | - |
| Data strobe (differential) |
|
| - | - | ||
| Data mask and data bus inversion | DDR4-DM0 ... DDR4-DM8 | - | - |
| Serial address inputs | DDR4-SA0 ... DDR4-SA2 | address range configuration |
on I²C bus | - | ||
| Control Signals | DDR4-CS_N0 / DDR4-CS_N1 | chip selest signal | - |
| DDR4-ODT0 / DDR4-ODT1 | On-die termination enable | - | |
| DDR4-RESET | nRESET | - | |
| DDR4-PAR | Command and address |
| parity input | - | |||
| DDR4-CKE0 / DDR4-CKE1 | Clock enable | - | ||
| DDR4-ALERT | CRC error flag | - | ||
| DDR4-ACT | Activation command input | - | ||
| DDR4-EVENT | Temperature event | - | ||
| I²C |
| - | 8-channel I²C switch U37 | - |
Table 40: DDR4 64-bit memory interface signals and pins
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.
CAN Interface
Figure X: CAN Interface
SD Card Interface
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Figure X: CAN Interface
SD Card Interface
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Figure X: SD Card Interface
Describe SD Card interface shortly here if the module has one...
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