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Figure X: Gigabit Ethernet Interface

PHY Pin	Connected to	Notes
MDC/MDIO	PS bank 502 MIO76, MIO77	-
PHY LED0..2	SC CPLD U27, bank 4, pin L5, L1, K1	see schematic for details, forwarded to RJ45 GbE MagJack J7
PHY_CLK125M	SC CPLD U27, bank 4, pin K2	125 MHz Ethernet PHY clock out
CONFIG	pulled up to PS_1V8	Configuration of PHY address LSB and VDDO level
RESETn	SC CPLD U27, bank 4, pin L6	Active low reset line
RGMII	PS bank 502 MIO64 ... MIO75	Reduced Gigabit Media Independent Interface
SGMII	-	Serial Gigabit Media Independent Interface
MDI	RJ45 GbE MagJack J13	Media Dependent Interface

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Figure X: USB3 Interface

The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Notes
DisplayPort Connector J12	MGT Lane	B505_TX2_P B505_TX2_N B505_TX3_P B505_TX3_N	PS GTR bank 505 Pins: PS_MGTRTXP2_505, W31 PS_MGTRTXN2_505, W32 PS_MGTRTXP3_505, V29 PS_MGTRTXN3_505, V30	Output	Multi gigabit highspeed data lane (only transmit pairs)	-
	Auxiliary Line	DP_TX_AUX_P DP_TX_AUX_N	LVDS Line Driver/Receiver, U30	-	Convert signal from single ended to LVDS Single ended signals: 'DP_AUX_TX', 'DP_AUX_RX', SC CPLD U27, bank 2, pins AA14, AB12	-
	Control Lines	DP_TX_HPD	SC CPLD U27, bank 2, pin AA15	Input	DisplayPort Hot Plug Detect	-
	Control Lines	DP_EN	LDO U29	-	3.3V Supply Voltage for DisplayPort	-

Table 39: DisplayPort signals and interfaces

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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

Connector	DDR4 SDRAM I/O Signal	Signal Schematic Name	Description	Connected to	Notes
DDR4 SO-DIMM Socket U13	Address inputs	DDR4-A0 ... DDR4-A16	-	PS DDR Bank 504	-
	Bank address inputs	DDR4-BA0 / DDR4-BA1	-		-
	Bank group inputs	DDR4-BG0 / DDR4-BG1	-		-
	Differential clocks	DDR4-CLK0_P DDR4-CLK0_N DDR4-CLK1_P DDR4-CLK1_N	2 x DDR4 clock		-
	Data input/output	DQ0 ... DQ63	-		-
	Check bit input/output	CB0 ... CB7	-		-
	Data strobe (differential)	DDR4-DQS0_P DDR4-DQS0_N ... DDR4-DQS8_P DDR4-DQS8_N	-		-
	Data mask and data bus inversion	DDR4-DM0 ... DDR4-DM8	-		-
	Serial address inputs	DDR4-SA0 ... DDR4-SA2	address range configuration on I²C bus		-
	Control Signals	DDR4-CS_N0 / DDR4-CS_N1	chip selest signal		-
		DDR4-ODT0 / DDR4-ODT1	On-die termination enable		-
		DDR4-RESET	nRESET		-
		DDR4-PAR	Command and address parity input		-
		DDR4-CKE0 / DDR4-CKE1	Clock enable		-
		DDR4-ALERT	CRC error flag		-
		DDR4-ACT	Activation command input		-
		DDR4-EVENT	Temperature event		-
	I²C	DDR4-SCL DDR4-SDA	-	8-channel I²C switch U37	-

Table 40: DDR4 64-bit memory interface signals and pins

Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.

CAN Interface

The TEB0911 board provides a CAN interface, the CAN transceiver is connected and operated by the SC CPLD:

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Figure X: CAN Interface

SD Card Interface

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Figure X: SD Card Interface

Describe SD Card interface shortly here if the module has one...

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The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

Connector	Signal Schematic Name	Connected to	Notes
D-SUB 9-pin male connector J3	CAN_H, pin 7	CAN Transceiver U48, pin 7	-
D-SUB 9-pin male connector J3	CAN_L, pin 2	CAN Transceiver U48, pin 6	-
6-pin male header J15	CAN_H, pin 4	CAN Transceiver U48, pin 7	-
6-pin male header J15	CAN_L, pin 3	CAN Transceiver U48, pin 6	-

Table 40: DDR4 64-bit memory interface signals and pins

SD Card Interface

The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:

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Table x: SD Card interface signals and connections.

4-Wire PWM FAN Connectors

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4-Wire PWM Fan Connectors

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497

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5

6

Figure X: 4-Wire PWM FAN Connectors

PLL Clock Interfaces

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SD Card Interface

The SD Card socket have following signal and pin assignment:

Connector	Signal Schematic Name	Connected to	Notes
SD Card Socket J11	SD_DAT0, J11-7	PS bank 501 Pins: MIO46 ... MIO51	-
	SD_DAT1, J11-8		-
	SD_DAT2, J11-9		-
	SD_DAT3, J11-1		-
	SD_CMD, J11-2		-
	SD_CK, J11-5		-
	SD_CD, J11-10	SC CPLD U27, bank 2, pin T11	Card Detect
	SD_WP, J11-11	SC CPLD U27, bank 2, pin T10	Write Protect

Table x: SD Card interface signals and connections

4-Wire PWM FAN Connectors

The TEB0911 offers 3x 4-wire PWM FAN connectors for optional cooling fans controlled by SC CPLD U27:

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Figure X: 4-Wire PWM FAN Connectors

Connector	Signal Schematic Name	Connected to	Notes
Fan Connector J2	F1PWM
	F1SENSE
	F1_EN
Fan Connector J23



Fan Connector J33

PLL Clock Interfaces

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Figure X: PLL Clock Interfaces

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family).

Figure X: PLL Clock Interfaces

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.

The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA - module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.

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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

...

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.

The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interfaceTable x: System Controller CPLD I/O pins.

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ForPut the detailed function of the pins and signals, the internal signal assignment and implemented logic, lookin link to the Wiki reference page SC CPLD of this module or into the bitstream filefirmware of the SC CPLD.
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   -->  -->

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin Name	Mode	Function	B2B Connector Pin	Default Configuration
PGOOD	Output	Power Good	J1-148	Active high when all on-module power supplies are working properly.
JTAGEN	Input	JTAG Select	J2-131	Low for normal operation.
..	..	..	..	..

Table x: System Controller CPLD I/O pins.

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
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HighHigh-speed USB ULPI PHY

USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).

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Table : Module absolute maximum ratings

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

...

Note
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage
Operating temperature

Table : Module recommended operating conditions

Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

Date	Revision	Notes	PCN	Documentation Link
-	01	Prototypes

Table : Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

HTML

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Ali Naseri

Initial document

...

Table : Module recommended operating conditions

Note
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Extended grade: 0°C to +85°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

...

Notes

...

01

...

Prototypes

Table : Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Put picture of actual PCB showing model and hardware revision number here...

Figure : Module hardware revision number.

Document Change History

HTML

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Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
  -->

Template revision 1.64
SD Card interface added.

Date	Revision	Contributors	Description
Page info
modified-date	modified-date
dateFormat	yyyy-MM-dd
John Hartfiel	Remove Link to Download
2017-11-10	v.58	Ali Naseri	PDF-Link to online version of the TRM fixed Online Link of download area fixed
2017-09-06	v.56	Jan Kumann
2017-09-02	v.54	Jan Kumann	DDR Memory section added.
2017-08-27	v.43	John Hartfiel	New template revision 1.6. Moved Boot Process between Overview and Signals, Interfaces and Pins section.
2017-08-16	v.42	Jan Kumann	New template revision 1.5 MGT Lanes section changed. Programmable PLL Clock section changed. "Figure" and "Table" labels added. Module variants and temperatures ranges sections improved. Comments added/changed, also formatted as italic now.
2017-08-07	v.32	Jan Kumann	Few corrections and cosmetic changes.
2017-07-14	v.25	John Hartfiel	Removed weight section update template version
2017-06-08	v.20	John Hartfiel	Add revision number and update document change history
2017-05-30	v.1	Jan Kumann	Initial document.
all	Jan Kumann, John Hartfiel

Table : Document change history

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Trenz Electronic Documentation

Versions Compared

Old Version 98

New Version 99

Key

CAN Interface

SD Card Interface

SD Card Interface

4-Wire PWM FAN Connectors

PLL Clock Interfaces

4-Wire PWM FAN Connectors

PLL Clock Interfaces

On-board Peripherals

System Controller CPLD

On-board Peripherals

System Controller CPLD

HighHigh-speed USB ULPI PHY

Recommended Operating Conditions

Recommended Operating Conditions

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History

Operating Temperature Ranges

Physical Dimensions

Revision History

Hardware Revision History

Document Change History