Page History

...

Lane	Bank	Type	Signal Name	B2B Pin	FPGA Pin
0	505	GTR	B505_RX0_P B505_RX0_N B505_TX0_P B505_TX0_N	JM3-26 JM3-28 JM3-25 JM3-27	PS_MGTRRXP0_505, F27 PS_MGTRRXN0_505, F28 PS_MGTRTXP0_505, E25 PS_MGTRTXN0_505, E26
1	505	GTR	B505_RX1_P B505_RX1_N B505_TX1_P B505_TX1_N	JM3-20 JM3-22 JM3-19 JM3-21	PS_MGTRRXP1_505, D27 PS_MGTRRXN1_505, D28 PS_MGTRTXP1_505, D23 PS_MGTRTXN1_505, D24
2	505	GTR	B505_RX2_P B505_RX2_N B505_TX2_P B505_TX2_N	JM3-14 JM3-16 JM3-13 JM3-15	PS_MGTRRXP0_505, B27 PS_MGTRRXN0_505, B28 PS_MGTRTXP0_505, C25 PS_MGTRTXN0_505, C26
3	505	GTR	B505_RX3_P B505_RX3_N B505_TX3_P B505_TX3_N	JM3-8 JM3-10 JM3-7 JM3-9	PS_MGTRRXP1_505, A25 PS_MGTRRXN1_505, A26 PS_MGTRTXP1_505, B23 PS_MGTRTXN1_505, B24

Table 4: MGT lanes.

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

...

Power Rail Name on B2B Connector	JM1 Pins	JM2 Pins	Direction	Notes
VIN	1, 3, 5	2, 4, 6, 8	Input	Supply voltage from the carrier board.
3.3V	-	10, 12	Output	Internal 3.3V voltage level.
3.3VIN	13, 15	-	Input	Supply voltage from the carrier board.
1.8V	39	-	Output	Internal 1.8V voltage level.
JTAG VREF	-	91	Output	JTAG reference voltage. Attention: Net name on schematic is "3.3VIN"
VCCO_64	-	7, 9	Input	High performance I/O bank voltage.
VCCO_65	-	5	Input	High performance I/O bank voltage.
VCCO_66	9, 11	-	Input	High performance I/O bank voltage.

...

Module Variant	MPSoC	RAM	SPI Flash	Temperature Range	Note
TE0820-02-02CG-1E	XCZU2CG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-03CG-1E	XCZU3CG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-02EG-1E	XCZU2EG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-03EG-1E	XCZU3EG-1SFVC784E	1 GByte DDR4	64 MByte	Extended
TE0820-02-02EG-1E3	XCZU2EG-1SFVC784E	1 GByte DDR4	64 MByte	Extended	2,5mm Samtec connector
TE0820-02-03EG-1E3	XCZU3EG-1SFVC784E	1 GByte DDR4	64 MByte	Extended	2,5mm Samtec connector

...

Table 19: Recommended operating conditions.

Note
See Xilinx datasheet DS925 for more information about absolute maximum and recommended operating ratings for the Zynq UltraScale+ chips.

...

Date	Revision	Notes	PCN Link	Documentation Link
2017-08-17	02	--			TE0820-02
2016-12-23	01	Prototype only			TE0820-01

Table 20: Hardware revision history table.

...

Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

John Hartfiel

Correction Power Rail Section

2017-11-20

v.51

John Hartfiel

Correction Default MIO Configuration Table

2017-11-10

v.50

John Hartfiel

Replace B2B connector section

2017-10-18

v.49

John Hartfiel

add eMMC section

2017-09-25

v.48

John Hartfiel

Correction in the "Board to Board (B2B) I/Os" section
Update in the "Variants Currently In Production" section

2017-09-18

v.47

John Hartfiel

Update PS MIO table

2017-08-30

v.46

Jan Kumann

MGT lanes section added.

2017-08-24

v.36

John Hartfiel

Correction in the "Key Features" section.

2017-08-21

v.34

John Hartfiel

"Initial delivery state" section updated.

2017-08-21

v.33

Jan Kumann

HW revision 02 block diagram added.
Power distribution and power-on sequence diagram added.
System Controller CPLD and DDR4 SDRAM sections added.
TRM update to the template revision 1.6
Weight section removed.
Few minor corrections.

2017-08-18

v.7

John Hartfiel

Style changes
Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
Correction of MIO SD Pin-out, System Controller chapter
Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version.

...

Trenz Electronic Documentation

Versions Compared

Old Version 54

New Version 55

Key