Page History

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FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J21 (FMC F)	I/O	12	6	Bank 44 HD	FMCAF_1V8	-
		28	14	SC CPLD U27 Bank 1	FMCAF_1V8	-
		68	34	SC CPLD U27 Bank 3	FMCAF_1V8	-
	I²C	2	-	I²C-Switch U37	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	4 (2 x RX/TX)	Bank 129 GTH	-	2x MGT lanes
	Clock Input	-	1	Bank 129 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT'

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FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J4 (FMC B)	I/O	24	12	Bank 47 HD	FMCBC_1V8	-
		20	10	Bank 48 HD	FMCBC_1V8	-
		24	12	Bank 49 HD	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 0	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 130 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 48 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 130 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 0	3.3VSB	'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT'

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FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J8 (FMC C)	I/O	20	10	Bank 50 HD	FMCBC_1V8	-
	I/O	68	34	Bank 67 HP	FMCBC_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 230 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 50 HD	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 230 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT'

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FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J7 (FMC D)	I/O	20	10	Bank 65 HP	FMCDE_1V8	-
	I/O	48	24	Bank 66 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 229 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 65 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 229 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT'

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FMC	Interfaces	I/O Signal Count	LVDS-pairs count	Connected to	VCCO bank Voltage	Notes
J6 (FMC E)	I/O	24	12	Bank 65 HP	FMCDE_1V8	-
	I/O	44	22	Bank 64 HP	FMCDE_1V8	-
	I²C	2	-	I²C-Switch U13	-	Muxed to MIO Bank 501 I²C Inteface
	JTAG	4	-	SC CPLD U27 Bank 2	3.3VSB	-
	MGT	-	8 (4 x RX/TX)	Bank 228 GTH	-	4x MGT lanes
	Clock Input	-	2	Bank 64 HP	-	2x Reference clock inputs to PL bank
	Clock Input	-	1	Bank 228 GTH	-	1x Reference clock input to MGT bank
	Control Signals	3	-	SC CPLD U27 Bank 2	3.3VSB	'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT'

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Figure X: Gigabit Ethernet Interfaceinterface

PHY Pin	Connected to	Notes
MDC/MDIO	PS bank 502 MIO76, MIO77	-
PHY LED0..2	SC CPLD U27, bank 4, pin L5, L1, K1	see schematic for details, forwarded to RJ45 GbE MagJack J7
PHY_CLK125M	SC CPLD U27, bank 4, pin K2	125 MHz Ethernet PHY clock out
CONFIG	pulled up to PS_1V8	Configuration of PHY address LSB and VDDO level
RESETn	SC CPLD U27, bank 4, pin L6	Active low reset line
RGMII	PS bank 502 MIO64 ... MIO75	Reduced Gigabit Media Independent Interface
SGMII	-	Serial Gigabit Media Independent Interface
MDI	RJ45 GbE MagJack J13	Media Dependent Interface

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draw.io Diagram

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Figure X: USB3 Interfaceinterface

The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

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draw.io Diagram

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Figure X: SFP+ Interfaceinterface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P B129_TX3_N B129_RX3_P B129_RX3_N	GTH bank 129 Pins: MGTHTXP3_129, G31 MGTHTXN3_129, G32 MGTHRXP3_129, F33 MGTHRXN3_129, F34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP0_SDA SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP0_RS1		Output	Reduced RX bandwidth	Low active
		SFP0_M-DEF0		Input	Module present / not present	Low active
		SFP0_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input	Loss of receiver signal	High active	-
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output	SFP Enabled / Disabled	Low active	-
SFP+ J9B	MGT Lane	B129_TX2_P B129_TX2_N B129_RX2_P B129_RX2_N	GTH bank 129 Pins: MGTHTXP2_129, H29 MGTHTXN2_129, H30 MGTHRXP2_129, H33 MGTHRXN2_129, H34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP1_SDA SFP1_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP1_RS1		Output	Reduced RX bandwidth	Low active
		SFP1_M-DEF0		Input	Module present / not present	Low active
		SFP1_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input	Loss of receiver signal	High active	-
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output	SFP Enabled / Disabled	Low active	-

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draw.io Diagram

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Figure X: SSD Interfaceinterface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N	PS GTR bank 505 Pins: PS_MGTRTXP0_505, AB29 PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 PS_MGTRTXN0_505, AB34	BiDir	Multi gigabit highspeed data lane	-	-
	Clock Input	SSD_RCLK_P SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	-	Reference clock signal	-	-
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	Output	LED Output	High active	-
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	Input	PCIe sleep state	Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	Input	PCIe reset input	Low active	-
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	Input	PCIe Link reactivation	Low active	-
		SSD1_CLKRQ	connect to GND	BiDir	PCIe Clock Request	Low active	-

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The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is feeded by connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.

draw.io Diagram

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Figure X: DisplayPort Interfaceinterface

Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

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draw.io Diagram

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Figure X: CAN Interfaceinterface

The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

Connector	Signal Schematic Name	Connected to	Notes
D-SUB 9-pin male connector J3	CAN_H, pin 7	CAN Transceiver U48, pin 7	-
D-SUB 9-pin male connector J3	CAN_L, pin 2	CAN Transceiver U48, pin 6	-
6-pin male header J15	CAN_H, pin 4	CAN Transceiver U48, pin 7	-
6-pin male header J15	CAN_L, pin 3	CAN Transceiver U48, pin 6	-

Table 4041: DDR4 64-bit memory interface signals and pins

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draw.io Diagram

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Figure X: SD Card Interfaceinterface

The SD Card socket have following signal and pin assignment:

Connector	Signal Schematic Name	Connected to	Notes
SD Card Socket J11	SD_DAT0, J11-7	PS bank 501 Pins: MIO46 ... MIO51	-
	SD_DAT1, J11-8		-
	SD_DAT2, J11-9		-
	SD_DAT3, J11-1		-
	SD_CMD, J11-2		-
	SD_CK, J11-5		-
	SD_CD, J11-10	SC CPLD U27, bank 2, pin T11	Card Detect
	SD_WP, J11-11	SC CPLD U27, bank 2, pin T10	Write Protect

Table x42: SD Card interface signals and connections

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draw.io Diagram

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Figure X: 4-Wire PWM FAN Connectorsconnectors

Connector

Signal Schematic Name

Connected to

Notes

Fan Connector

J2

F1PWM

SC CPLD U27, bank 0, pin E10

-

F1SENSE

SC CPLD U27, bank 0, pin D11

-

F1_EN

Fan Connector

J23

SC CPLD U27, bank 0, pin C8	Controls 12V Load Switch
Fan Connector

J33

J23

PLL Clock Interfaces

F2PWM	SC CPLD U27, bank 0, pin D9	-
F2SENSE	SC CPLD U27, bank 0, pin G12	-
F2_EN	SC CPLD U27, bank 0, pin B4	Controls 12V Load Switch
Fan Connector J33	F3PWM	SC CPLD U27, bank 0, pin B13	-
	F3SENSE	SC CPLD U27, bank 0, pin A13	-
	F3_EN	SC CPLD U27, bank 0, pin A12	Controls 12V Load Switch

Table 43: 4-wire PWM fan connectors signals and pins

PLL Clock Interfaces

The programmable 10-output reference clock generator U17 can be accessed through its I²C interface to be programed. The I²C interface is connected to the Zynq MPSoc via I²C switch U13 and to pin header J22.

With the SMA Coaxial connector J25 the clock generator can be supplied with an external clock signal.

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Figure X: PLL clock interfaces

Connector

Signal Schematic Name

Connected to

Notes

Pin Header

J22

PLL_SCL

clock generator U17, pin 16

PS_1V8 VCCIO

PLL_SDA

clock generator U17, pin 18

SMA Coax

J25

CLK_PLL_IN

clock generator U17, pin 1

-

Figure X: PLL Clock InterfacesTable 44: Clock generator Si5345A external interfaces

On-board Peripherals

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<!-- Components on the Module, like Flash, PLL, PHY... -->

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EEPROM Modell	Schematic Designator	Memory Density	Purpose
24LC128-I/ST	U24	128 Kbit	user
24AA025E48T-I/OT	U36	2 Kbit	user
24AA025E48T-I/OT	U41	2 Kbit	user
24AA025E48T-I/OT	U42	2 Kbit	user
24LC128-I/ST	U5	128 Kbit	USB3.0 Hub U4 configuration memory

Table 21: On-board configuration EEPROMs overview

	user
24LC128-I/ST	U5	128 Kbit	USB3.0 Hub U4 configuration memory

Table 21: On-board configuration EEPROMs overview

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

CAN FD Transceiver

On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.

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Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

MAC Address EEPROM

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Oscillators

The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

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Trenz Electronic Documentation

Versions Compared

Old Version 99

New Version 100

Key

PLL Clock Interfaces

PLL Clock Interfaces

On-board Peripherals

CAN FD Transceiver

MAC Address EEPROM

Oscillators