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Figure X: PLL clock interfaces

Table 44: Clock generator Si5345A external interfaces

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System Controller CPLD

The TEB0911 UltraRack is equipped with one System Controller CPLD (U2) is provided by CPLDs - Lattice Semiconductor LCMXO2-256HC 7000HC (MachXO2 Product Family) with the schematic designators U27. The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.
For detailed information, refer to the reference page of the SC CPLD firmware of this moduleboard.

The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.

The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.

The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.

Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO pins. The signals of these pins are forwarded by the SC CPLD to control some of the on board peripherals.

Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS ( MIO ), PL bank pins and I²C interface..

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