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Figure X: PLL clock interfaces
| Connector | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
Pin Header J22 | PLL_SCL | clock generator U17, pin 16 | PS_1V8 VCCIO |
| PLL_SDA | clock generator U17, pin 18 | ||
SMA Coax J25 | CLK_PLL_IN | clock generator U17, pin 1 | - |
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Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.For detailed information, refer to the reference page of the SC CPLD firmware of this board.
The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO pins. The signals of these pins are forwarded by the SC CPLD to control some of the on board peripherals.
Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins:
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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.2
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Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
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