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High-speed
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USB2 ULPI PHY
USB PHY (U9) USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10)U16.
| PHY Pin | Connected to | Notes |
|---|---|---|
| ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY |
| REFCLK | - | 52MHz from on board oscillator (U9)U16 |
| REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) |
| RESETB | SC CPLD U17U27, bank 4, Pin: M2 | Low active USB USB2 PHY Reset (pulled-up to PS_1.8V). |
| DP, DM | 4-port USB3 .0 Hub U4 | USB2 .0 data lane |
| CPEN | - | External USB power switch active-high enable signal |
| VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic |
| ID | - | For an A-device connect to the ground. For a B-device, leave floating |
Table 1745: USB PHY interface connectionsHi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
4-port USB3
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Hub
On the carrier TEB0911 board there are up to 4 2 USB3 .0 Super Speed ports available, which are also downward compatible to USB2 .0 High Speed ports. The USB3 .0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3 .0 Hub controller U4. The pin-strap configuration option of the USB3 .0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is are also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16U37.
On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3 .0 data lane. For the USB2 .0 interface, the controller is connected to the on-board USB2 .0 PHY U9U15. The USB2 .0 PHY is connected per via ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.
The USB3 .0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.
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On-board Gigabit Ethernet PHY (U12) U20 is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.U21.
| PHY Pin | Connected to | Notes |
|---|---|---|
| MDC/MDIO | PS bank MIO76, MIO77 | - |
| PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
| PHY_LED2 / INTn: | SC CPLD U17, pin 85 | Active low interrupt line |
| PHY_CLK125M | SC CPLD U17U27, bank 4, pin 70K2 | 125 MHz Ethernet PHY clock out |
| CONFIG | SC CPLD U17, pin 65 | Configuration of PHY address LSB and VDDO level |
| RESETn | SC CPLD U17, pin 62 | Active low reset line |
| RGMII | PS bank MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
| SGMII | - | Serial Gigabit Media Independent Interface |
| MDI | RJ45 GbE MagJack J7 | Media Dependent Interface |
Table 1846: Ethernet PHY interface connectionsOn-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
8-Channel I²C Switches
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
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Overview
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