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Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
D-SUB 9-pin J3 | CAN_H, pin 7 | CAN Transceiver U48, pin 7 | - |
CAN_L, pin 2 | CAN Transceiver U48, pin 6 | - | |
6-pin male header J15 | CAN_H, pin 4 | CAN Transceiver U48, pin 7 | - |
CAN_L, pin 3 | CAN Transceiver U48, pin 6 | - | |
CAN Transceiver | Signal Schematic Name | Connected to | Notes |
TCAN337 U48 | CAN_TX | SC CPLD U27, bank 0, pin C16 | 3.3V VCCIO |
CAN_RX | SC CPLD U27, bank 0, pin B15 | 3.3V VCCIO | |
CAN_S | SC CPLD U27, bank 0, pin C15 | 3.3V VCCIO | |
CAN_FAULT | SC CPLD U27, bank 0, pin D15 | 3.3V VCCIO |
Table 41: CAN Table 41: DDR4 64-bit memory interface signals and pins
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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
The PS_1V8 and VCCINT_0V85 voltage levels are monitored by the voltage monitor circuit U89, which generates the POR_B signal to RESET the board. A manual reset is also possible by driving the pin 'MR' on SC CPLD, bank 4, pin L7 to GND.
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On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21.
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The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U27, bank 4, pin K2.
8-Channel I²C Switches
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEB0911 board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.
Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.
The on-board I2C bus works with reference voltage 3.3V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) and configured as master.
MIO | Signal Schematic Name | Notes |
---|---|---|
38 | I2C_SCL | 3.3V reference voltage |
39 | I2C_SDA | 3.3V reference voltage |
Table 46: MIO-pin assignment of the module's I2C interface
The I²C switches can be reseted simultanously by the pin 'I2C_RST', which is connected to SC CPLD U27, bank 4 pin L2 with low active logic.
I2C addresses (7 bit without read/write-bit) for on-board slave devices are listed in the table below:
I²C Slave Devices connected to MPSoC I²C Interface | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
---|---|---|---|
8-channel I²C switch U13 | - | 0x76 | I2C_SDA / I2C_SCL |
8-channel I²C switch U37 | - | 0x77 | I2C_SDA / I2C_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U13 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
FMC Connector J7 (FMC D) | 2 | 0x50 | FMCD_SDA / FMCD_SCL |
FMC Connector J6 (FMC E) | 3 | 0x50 | FMCE_SDA / FMCE_SCL |
FMC Connector J4 (FMC B) | 4 | 0x50 | FMCB_SDA / FMCB_SCL |
FMC Connector J8 (FMC C) | 5 | 0x50 | FMCC_SDA / FMCC_SCL |
PLL clock generator U17 Si5345A | 6 | 0x69 | PLL_SDA / PLL_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U37 |
Table 46: Ethernet PHY interface connections
8-Channel I²C Switches
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEB0911 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.
Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.
The I2C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) configured as master.
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I2C addresses for on-board slave devices are listed in the table below:
I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
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FMC Connector J10 (FMC A) | 1 | 0x50 | FMCA |
_SDA / |
FMCA_SCL |
Switch
Position
FMC Connector J21 (FMC F) | 2 | 0x50 | FMCF_SDA / FMCF_SCL |
SFP+ Connector J9A | 3 | 0x50 / 0x51 | SFP0_SDA / SFP0 |
_SCL |
8-bit I²C IO Expander |
U86 (SPF+ connector control signals) | 3 | 0x27 | SFP0 |
_SDA / |
SFP0_SCL |
SFP+ Connector |
J9B |
4 | 0x50 / 0x51 |
SFP1_SDA / SFP1_SCL |
PLL clock generator U12 Si5338A | 5 | 0x70 | MEM_SDA / |
MEM_SCL |
Configuration EEPROM |
U83 | 5 |
0x51 | MEM_SDA / MEM_SCL |
Configuration EEPROM |
U45 | 5 | 0x52 | MEM_SDA / MEM_SCL |
Configuration EEPROM |
U60 | 5 |
0x53 | MEM_SDA / MEM_SCL |
Configuration EEPROM U57 | 5 |
0x57 | MEM_SDA / MEM_SCL |
SC CPLD U27 | 5 |
user configurable | MEM_SDA / MEM_SCL |
DDR4 SODIMM I²C interface | 6 | module dependent |
DDR4-SDA / |
DDR4-SCL |
USB3 |
Hub |
U4 | 7 |
0x60 | USBH_SDA / USBH_SCL |
USB3 |
Hub configuration EEPROM U5 | 7 |
0x51 | USBH_SDA / USBH_SCL |
Switch
Position
Table 20: On-board peripherals' I2C-interfaces device slave addresses
Configuration EEPROMs
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
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Table 46: On-board peripherals' I2C-interfaces device slave addresses
Configuration EEPROMs
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
EEPROM Modell | Schematic Designator | Memory Density | Purpose |
---|---|---|---|
24LC128-I/ST | U57 | 128 Kbit | user |
24AA025E48T-I/OT | U60 | 2 Kbit | user |
24AA025E48T-I/OT | U45 | 2 Kbit | user |
24AA025E48T-I/OT | U83 | 2 Kbit | user |
24LC128-I/ST | U5 | 128 Kbit | USB3 Hub U4 configuration memory |
Table 47: On-board configuration EEPROMs overview
CAN FD Transceiver
On-board CAN FD (Flexible Data Rate) transceiver U48 is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U27, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD.
On-board Flash Memory
On-board QSPI flash memory U24 and U25 on the TEB0911 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The TEB0911 board is also
Table 21: On-board configuration EEPROMs overview
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
CAN FD Transceiver
On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.
eMMC Memory
The TEB0911 UltraRack board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.
Quad SPI Flash Memory
.
IC | Name | Memory Density | Designator | Connected to | Notes |
---|---|---|---|---|---|
QSPI Flash | N25Q256A11E1240E | 256 Mbit (32 MByte) | U24 | QSPI0: MIO0 ... MIO5 | dual parallel booting possible, 64 MByte total QSPI Flash memory connected via Dual QSPI MIO0 ... MIO12 |
QSPI Flash | N25Q256A11E1240E | 256 Mbit (32 MByte) | U25 | QSPI0: MIO7 ... MIO12 | |
eMMC Flash | MTFC4GACAJCN-4M IT | 32 Gbit (4 GByte) | U26 | SD0 eMMC: MIO13 ... MIO23 | bootable eMMC |
Table 48: On-board Flash memory ICs overview
Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.
MIO | Signal Name | U24 Pin | MIO | Signal Name | U25 Pin | MIO | Signal Name | U25 Pin | ||
---|---|---|---|---|---|---|---|---|---|---|
0 | SPI Flash CLK | B2 | 7 | SPI Flash CS | C2 | 13 | MMC D0 | H3 | ||
1 | SPI Flash IO1 | D2 | 8 | SPI Flash IO0 | D3 | 14 | MMC D1 | H4 | ||
2 | SPI Flash IO2 | C4 | 9 | SPI Flash IO1 | D2 | 15 | MMC D2 | H5 | ||
3 | SPI Flash IO3 | D4 | 10 | SPI Flash IO2 | C4 | 16 | MMC D3 | J2 | ||
4 | SPI Flash IO0 | D3 | 11 | SPI Flash IO3 | D4 | 17 | MMC D4 | J3 | ||
5 | SPI Flash CS | C2 | 12 | SPI Flash CLK | B2 | 18 | MMC D5 | J4 | ||
19 | MMC D6 | J5 | ||||||||
20 | MMC D7 | J6 | ||||||||
21 | MMC CMD | W5 | ||||||||
22 | MMC CLKR | W6 | ||||||||
23 | MMC RST | U5 |
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.Table 49: PS MIO pin assignment of the Flash memory ICs
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SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
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Figure : Module power-on diagram.
Voltage Monitor Circuit
If the module has one, describe it here...Temp core dc
Power Rails
NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.
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