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The PS_1V8 and VCCINT_0V85 voltage levels are monitored by the voltage monitor circuit U89, which generates the POR_B signal to RESET reset the board if voltage failure occurs. A manual resetis also possible by driving the pin 'MR' on SC CPLD, bank 4, pin L7 to GND.

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The TEB0911 board is also equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.

IC	Name	Memory Density

Designator

	Connected to	Notes
QSPI Flash U24	N25Q256A11E1240E	256 Mbit (32 MByte)

U24

QSPI0: MIO0 ... MIO5

dual parallel booting possible, 64 MByte total QSPI Flash memory

connected via Dual QSPI MIO0 ... MIO12

QSPI Flash U25

N25Q256A11E1240E

256 Mbit (32 MByte)

U25

	QSPI0: MIO7 ... MIO12
eMMC Flash U26	MTFC4GACAJCN-4M IT	32 Gbit (4 GByte)

U26

SD0 eMMC: MIO13 ... MIO23

bootable eMMC

Table 48: On-board Flash memory ICs overview

Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.

MIO	Signal Name	U24 Pin	MIO	Signal Name	U25 Pin	MIO	Signal Name	U25 Pin
0	SPI Flash CLK	B2	7	SPI Flash CS	C2	13	MMC D0	H3
1	SPI Flash IO1	D2	8	SPI Flash IO0	D3	14	MMC D1	H4
2	SPI Flash IO2	C4	9	SPI Flash IO1	D2	15	MMC D2	H5
3	SPI Flash IO3	D4	10	SPI Flash IO2	C4	16	MMC D3	J2
4	SPI Flash IO0	D3	11	SPI Flash IO3	D4	17	MMC D4	J3
5	SPI Flash CS	C2	12	SPI Flash CLK	B2	18	MMC D5	J4
						19	MMC D6	J5
						20	MMC D7	J6
						21	MMC CMD	W5
						22	MMC CLKR	W6
						23	MMC RST	U5

Table 49: PS MIO pin assignment of the Flash memory ICs

Note
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Oscillators

The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:

Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U10U22	USB0PS_RCLKCLK	5233.000000 333333 MHz	USB 2.0 transceiver PHY U9Zynq MPSoC PS Config Bank 503, pin 26U24
SiTime SiT8008BI SiT8008AI oscillator, U13U16	ETHUSB_CLK	2552.000000 MHz	Gigabit Ethernet USB2 transceiver PHY U12U15, pin 3426
Kyocera CX3225SB26000, Y3SiTime SiT8008BI oscillator, U7	-	2526.000000 000 MHz	Quad PLL clock generator U35, pin 3
DSC1123 oscillator, U23	B505_CLK1	150.0000 MHz	PS GT Bank, dedicated for SATA interface
DSC1123 oscillator, U6 optional, not equipped	B505_CLK0	100.0000 MHz	PS GT Bank, dedicated for USB interface
4-port USB3 Hub U4, pin 68/69
Kyocera CX3225SB26000, Y2	XAXB_P XAXB_N	54.000 MHz	PLL clock generator U17, pin 8/9
SiTime SiT8008BI oscillator, U21	ETH_CLKIN	25.000000 MHz	Gigabit Ethernet PHY U20, pin 34
SiTime SiT8008AI oscillator, U87Silicon Labs 570FBB000290DG, U45 optional, not equipped	B47_L5 (LVDS)	250.MHz	CLK_SC	25.000000 MHz	System Controller CPLD U27, bank 2, pin AA9PL Bank clock capable input pins
SiTime SiT8008BI oscillator, U25U18	CLKIN0_CPLDP	25.576000 000000 MHz	System Controller CPLD U35, pin 128

Table 16: Reference clock signal oscillators

Programmable Clock Generator Si5338A

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

PLL clock generator U17, pin 63

SiTime SiT8008AI oscillator, U85

-

25.000000 MHz

PLL clock generator U12, pin 3

DSC1123 oscillator, U92

optional, not equipped

B505_CLK3_P
B505_CLK3_N

100.0000 MHz

PS GTR Bank 505 Lane 3, dedicated for DisplayPort,
Pin U31, U32

Table 50: Reference clock signal oscillators

Programmable Clock Generator Si5338A

There is a Si5338A U12, Silicon Labs I²C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.

Si5338A Pin	Si5338A Pin	Signal Name / Description	Connected To	Direction	Note
IN1	CLK8_N	U17, pin 54	Input	Differential reference clock input from PLL clock generator U17
IN2	CLK8_P	U17, pin 53	Input		-	Not connected.	Input	Not used.	IN2	-	GND	Input	Not used.
IN3	Reference input clock.	U3U85, pin 3	Input	25.000000 MHz oscillator, Si8208AI.Si8008AI
IN4	-	GND	InputI²C slave device address LSB.	LSB (pin 'IN4') of the default I²C-adress 0x70 not set
IN5	-	Not connected.	Input	Not used.
IN6	-	GND	Input	Not used.
CLK0A	CLK1SSD_RCLK_P	U1U2, R23pin 55	OutputFPGA bank 45.	NGFF M.2 PCIe socket (Key M), dedicated as SSD interface
CLK0B	CLK1SSD_RCLK_N	U1U2, P23pin 53	Output	NGFF M.2 PCIe socket (Key M), dedicated as SSD interface	FPGA bank 45.
CLK1A	MGTB505_CLK1CLK2_N	U1, V5pin U27	OutputFPGA MGT bank 225 reference clock.	PS GTR Bank 505 Lane 2, dedicated for DisplayPort,
CLK1B	MGTB505_CLK1CLK2_P	U1, V6pin U28	OutputFPGA MGT bank 225 reference clock.	PS GTR Bank 505 Lane 2, dedicated for DisplayPort,
CLK2A	MGTB505_CLK3CLK1_N	U1, AB5pin W27	OutputFPGA MGT bank 224 reference clock.	PS GTR Bank 505 Lane 1, dedicated for USB3 interface
CLK2B	MGTB505_CLK3CLK1_P	U1, AB6pin W28	Output	PS GTR Bank 505 Lane 1, dedicated for USB3 interface	FPGA MGT bank 224 reference clock.
CLK3A	B505_CLK0_P	U1, pin T24AA27	OutputFPGA bank 45.	PS GTR Bank 505 Lane 0, dedicated for SSD interface
CLK3B	B505_CLK0_N	U1, pin T25AA28	OutputFPGA bank 45.	PS GTR Bank 505 Lane 0, dedicated for SSD interface

Table 51: Programmable quad PLL clock generator inputs and outputs.

Programmable Clock Generator Si5345A

Oscillators

The module has following reference clock signals provided by Following table shows on-board oscillators and external source from carrier board:

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Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

Si5345A Pin	Signal Name / Description	Connected To	Direction	Note
IN1 IN2	CLK8_N	U17, pin 54	Input	Differential reference clock input from PLL clock generator U17
IN1 IN2	CLK8_P	U17, pin 53	Input
IN3 IN4	Reference input clock	U85, pin 3	Input	25.000000 MHz oscillator, Si8008AI
IN3 IN4	-	GND	Input	I²C slave device address LSB
IN5 IN6	-	Not connected	Input	Not used
IN5 IN6	-	GND	Input	Not used
CLK0A CLK0B	SSD_RCLK_P	U2, pin 55	Output	NGFF M.2 PCIe socket (Key M), dedicated as SSD interface
CLK0A CLK0B	SSD_RCLK_N	U2, pin 53	Output	NGFF M.2 PCIe socket (Key M), dedicated as SSD interface
CLK1ACLK1B	B505_CLK2_N	U1, pin U27	Output	PS GTR Bank 505 Lane 2, dedicated for DisplayPort
CLK1ACLK1B	B505_CLK2_P	U1, pin U28	Output	PS GTR Bank 505 Lane 2, dedicated for DisplayPort
CLK2ACLK2B	B505_CLK1_N	U1, pin W27	Output	PS GTR Bank 505 Lane 1, dedicated for USB3 interface
CLK2ACLK2B	B505_CLK1_P	U1, pin W28	Output	PS GTR Bank 505 Lane 1, dedicated for USB3 interface
CLK3ACLK3B	B505_CLK0_P	U1, pin AA27	Output	PS GTR Bank 505 Lane 0, dedicated for SSD interface
CLK3ACLK3B


	B505_CLK0_N	U1, pin AA28	Output

Input	Connected to	Frequency	Notes
IN0	On-board Oscillator U18	25.000000 MHz	-
IN1	B2B Connector pins J2-3, J2-1 (differential pair)	User	AC decoupling required on base
IN2	B2B Connector pins J3-66, J3-68 (differential pair)	User	AC decoupling required on base
IN3	OUT9	User	Loop-back from OUT9
OUT0	B2B Connector pins J2-3, J2-1 (differential pair)	User	Default off
OUT1	B230 CLK0	User	Default off
OUT2	B229 CLK1	User	Default off
OUT3	B228 CLK1	User	Default off
OUT4	B505 CLK2	User	Default off
OUT5	B505 CLK3	User	Default off
OUT6	B128 CLK0	User	Default off
OUT7	B2B Connector pins J2-7, J2-9 (differential pair)	User	Default off
OUT8	B2B Connector pins J2-13, J2-15 (differential pair)	User	Default off
OUT9	IN3 (Loop-back)	User	Default off
XA/XB	Quartz (Y1)	50.000 MHz	-

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On-board LEDs

LED	Color	Connected to	Description and Notes
D1	Green
..	..	..	..

Table 53: On-board LEDs.

User Buttons

Configuration DIP-switches

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Table : Module power rails.

Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.

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Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
500 (MIO0)	PS_1.8V	1.8V	-
501 (MIO1)	PS_1.8V	1.8V	-
502 (DDR3)	1.35V	1.35V	-
12 HR	VCCIO_12	User	HR: 1.2V to 3.3V
13 HR	VCCIO_13	User	HR: 1.2V to 3.3V
33 HP	VCCIO_33	User	HP: 1.2V to 1.8V
34 HP	VCCIO_34	User	HP: 1.2V to 1.8V
35 HP	VCCIO_35	User	HP: 1.2V to 1.8V

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Trenz Electronic Documentation

Versions Compared

Old Version 106

New Version 107

Key

Oscillators

Programmable Clock Generator Si5338A

Programmable Clock Generator Si5338A

Programmable Clock Generator Si5345A

Oscillators

On-board LEDs

User Buttons

Configuration DIP-switches

Bank Voltages